From: Neha Malcom Francis <n-francis@ti.com>
Date: Tue, 30 Jan 2024 10:23:56 +0000 (+0530)
Subject: arm: mach-k3: j721s2_init: Support less than max DDR controllers
X-Git-Tag: v2025.01-rc5-pxa1908~662^2~3
X-Git-Url: http://git.dujemihanovic.xyz/img/static//%22brlog.php?a=commitdiff_plain;h=94cfc6fc96d2e718026d6aed9471994489a192f0;p=u-boot.git

arm: mach-k3: j721s2_init: Support less than max DDR controllers

The number of DDR controllers to be initialised and used should depend
on the device tree with the constraint of the maximum number of
controllers the device supports. Since J721S2 has multiple (2)
controllers, instead of hardcoding the number of probes, move to
depending on the device tree UCLASS_RAM nodes present.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
---

diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index fb0708bae1..3374889558 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -228,7 +228,7 @@ void k3_mem_init(void)
 			panic("DRAM 0 init failed: %d\n", ret);
 
 		ret = uclass_next_device_err(&dev);
-		if (ret)
+		if (ret && ret != -ENODEV)
 			panic("DRAM 1 init failed: %d\n", ret);
 	}
 	spl_enable_cache();