From: Simon Glass <sjg@chromium.org>
Date: Sun, 16 Jul 2023 03:39:13 +0000 (-0600)
Subject: x86: Make sure that the LPC is active before SDRAM init
X-Git-Tag: v2025.01-rc5-pxa1908~938^2~6
X-Git-Url: http://git.dujemihanovic.xyz/img/static/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=dac1fa5c197ae30a60b2ce7489051359b9c8ebea;p=u-boot.git

x86: Make sure that the LPC is active before SDRAM init

Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index ba3434b055..b6812bb8ca 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -65,6 +65,8 @@ static int set_max_freq(void)
 
 static int x86_spl_init(void)
 {
+	struct udevice *dev;
+
 #ifndef CONFIG_TPL
 	/*
 	 * TODO(sjg@chromium.org): We use this area of RAM for the stack
@@ -114,6 +116,13 @@ static int x86_spl_init(void)
 		return ret;
 	}
 #endif
+	/* probe the LPC so we get the GPIO_BASE set up correctly */
+	ret = uclass_first_device_err(UCLASS_LPC, &dev);
+	if (ret && ret != -ENODEV) {
+		log_debug("lpc probe failed\n");
+		return ret;
+	}
+
 	ret = dram_init();
 	if (ret) {
 		log_debug("dram_init() failed (err=%d)\n", ret);