ARM: dts: stm32: Adjust PLL4 settings on AV96 again

PLL4Q is supplying both FDCAN and LTDC. In case HDMI is in use, the
50 MHz generated from PLL4Q cannot be divided well enough to produce
accurate clock for HDMI pixel clock. Adjust it to generate 74.25 MHz
instead. The PLL4P/PLL4R are generating 99 MHz instead of 100 MHz,
which is in tolerance for the SDMMC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Gerald Baeza <gerald.baeza@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index 7529068c517ee22d395a8af2fb631a0310f47d9b..c73318488d0dbae37a0f9990ba0563895e133170 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -132,11 +132,11 @@
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
+       /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
        pll4: st,pll@3 {
                compatible = "st,stm32mp1-pll";
                reg = <3>;
-               cfg = < 1 49 5 11 5 PQR(1,1,1) >;
+               cfg = < 3 98 5 7 5 PQR(1,1,1) >;
                u-boot,dm-pre-reloc;
        };
 };