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(parent: 55aa0be) | patch
armv8/mmu: Set bits marked RES1 in TCR
authorThierry Reding <treding@nvidia.com>
Thu, 20 Aug 2015 09:52:14 +0000 (11:52 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 15 Oct 2015 12:46:43 +0000 (14:46 +0200)
commitad3d6e88a1a4e6aacc55b39c2bad1528100784c0
tree0e6da861d32909eb34dce4f2c20d30d803d0f2eatree | snapshot
parent55aa0bed9803b8a5bd3e462fd712741c2e1cff1bcommit | diff
armv8/mmu: Set bits marked RES1 in TCR

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.

For EL1, only bit 23 is not reserved, so only write bit 31 as 1.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/cpu/armv8/cache_v8.c diff | blob | history
arch/arm/include/asm/armv8/mmu.h diff | blob | history
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