From 2827d64774e7de9680ccd0b283856cc28f78a17f Mon Sep 17 00:00:00 2001
From: Saksham Jain <saksham.jain@nxp.com>
Date: Wed, 23 Mar 2016 16:24:33 +0530
Subject: [PATCH] armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFG
Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 10 ++++++++++
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 ++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 35d59081a5..00916f5c71 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -70,6 +70,16 @@
/* SFP */
#define CONFIG_SYS_FSL_SFP_VER_3_4
#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+
/* Cache Coherent Interconnect */
#define CCI_MN_BASE 0x04000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 6f1b144649..e8e3b91d3d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -76,6 +76,14 @@
/* SFP */
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x07000000)
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x07010000)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
+
+
/* PCIe */
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
@@ -212,6 +220,8 @@ struct ccsr_gur {
#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
+#define RCW_SB_EN_REG_INDEX 9
+#define RCW_SB_EN_MASK 0x00000400
u8 res_180[0x200-0x180];
u32 scratchrw[32]; /* Scratch Read/Write */
--
2.39.5