From ffdc71bc0977c1e6b7b6e6a5a005e1f77213bf21 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Mon, 10 May 2021 17:08:16 +0800 Subject: [PATCH] Revert "riscv: cpu: fu740: clear feature disable CSR" This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/fu540/spl.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c index 1740ef98b6..45657b7909 100644 --- a/arch/riscv/cpu/fu540/spl.c +++ b/arch/riscv/cpu/fu540/spl.c @@ -6,9 +6,6 @@ #include #include -#include - -#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -24,15 +21,3 @@ int spl_soc_init(void) return 0; } - -void harts_early_init(void) -{ - /* - * Feature Disable CSR - * - * Clear feature disable CSR to '0' to turn on all features for - * each core. This operation must be in M-mode. - */ - if (CONFIG_IS_ENABLED(RISCV_MMODE)) - csr_write(CSR_U74_FEATURE_DISABLE, 0); -} -- 2.39.5