From f020cff02b8b5ca6ae850a12128b112b925589ad Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Thu, 29 Sep 2022 12:35:49 -0500 Subject: [PATCH] arm: dts: k3-am64-evm: EMIF tool update to v0.08.40 for 1600MT/s DDR4 Move to latest DDR4 1600MT/s for k3-am64-evm based on EMIF tool v0.08.40. Signed-off-by: Dave Gerlach Signed-off-by: Anand Gadiyar --- arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi | 122 +++++++++++---------- 1 file changed, 62 insertions(+), 60 deletions(-) diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi index 9a008df750..491412119b 100644 --- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi +++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0 - * This file was generated on Oct 26 2020 - * DDR4 Frequency = 800MHz (1600MTs) + * This file was generated with the + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time) + * DDR Type: DDR4 + * Frequency = 800MHz (1600MTs) * Density: 16Gb * Number of Ranks: 1 */ @@ -49,11 +51,11 @@ #define DDRSS_CTL_35_DATA 0x00000000 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 -#define DDRSS_CTL_38_DATA 0x04000918 +#define DDRSS_CTL_38_DATA 0x0400091C #define DDRSS_CTL_39_DATA 0x1C1C1C1C -#define DDRSS_CTL_40_DATA 0x04000918 +#define DDRSS_CTL_40_DATA 0x0400091C #define DDRSS_CTL_41_DATA 0x1C1C1C1C -#define DDRSS_CTL_42_DATA 0x04000918 +#define DDRSS_CTL_42_DATA 0x0400091C #define DDRSS_CTL_43_DATA 0x1C1C1C1C #define DDRSS_CTL_44_DATA 0x05050404 #define DDRSS_CTL_45_DATA 0x00002706 @@ -215,22 +217,22 @@ #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 -#define DDRSS_CTL_204_DATA 0x00041400 +#define DDRSS_CTL_204_DATA 0x00042400 #define DDRSS_CTL_205_DATA 0x00000301 #define DDRSS_CTL_206_DATA 0x00000000 -#define DDRSS_CTL_207_DATA 0x00000414 +#define DDRSS_CTL_207_DATA 0x00000424 #define DDRSS_CTL_208_DATA 0x00000301 #define DDRSS_CTL_209_DATA 0x00000000 -#define DDRSS_CTL_210_DATA 0x00000414 +#define DDRSS_CTL_210_DATA 0x00000424 #define DDRSS_CTL_211_DATA 0x00000301 #define DDRSS_CTL_212_DATA 0x00000000 -#define DDRSS_CTL_213_DATA 0x00000414 +#define DDRSS_CTL_213_DATA 0x00000424 #define DDRSS_CTL_214_DATA 0x00000301 #define DDRSS_CTL_215_DATA 0x00000000 -#define DDRSS_CTL_216_DATA 0x00000414 +#define DDRSS_CTL_216_DATA 0x00000424 #define DDRSS_CTL_217_DATA 0x00000301 #define DDRSS_CTL_218_DATA 0x00000000 -#define DDRSS_CTL_219_DATA 0x00000414 +#define DDRSS_CTL_219_DATA 0x00000424 #define DDRSS_CTL_220_DATA 0x00000301 #define DDRSS_CTL_221_DATA 0x00000000 #define DDRSS_CTL_222_DATA 0x00000000 @@ -247,12 +249,12 @@ #define DDRSS_CTL_233_DATA 0x00000000 #define DDRSS_CTL_234_DATA 0x00000000 #define DDRSS_CTL_235_DATA 0x00000000 -#define DDRSS_CTL_236_DATA 0x00000401 -#define DDRSS_CTL_237_DATA 0x00000401 -#define DDRSS_CTL_238_DATA 0x00000401 -#define DDRSS_CTL_239_DATA 0x00000401 -#define DDRSS_CTL_240_DATA 0x00000401 -#define DDRSS_CTL_241_DATA 0x00000401 +#define DDRSS_CTL_236_DATA 0x00001401 +#define DDRSS_CTL_237_DATA 0x00001401 +#define DDRSS_CTL_238_DATA 0x00001401 +#define DDRSS_CTL_239_DATA 0x00001401 +#define DDRSS_CTL_240_DATA 0x00001401 +#define DDRSS_CTL_241_DATA 0x00001401 #define DDRSS_CTL_242_DATA 0x00000493 #define DDRSS_CTL_243_DATA 0x00000493 #define DDRSS_CTL_244_DATA 0x00000493 @@ -341,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x00000000 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01000000 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000100 #define DDRSS_CTL_333_DATA 0x00010000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -386,8 +388,8 @@ #define DDRSS_CTL_372_DATA 0x06060C06 #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x02000000 -#define DDRSS_CTL_375_DATA 0x03020101 -#define DDRSS_CTL_376_DATA 0x00000303 +#define DDRSS_CTL_375_DATA 0x05020101 +#define DDRSS_CTL_376_DATA 0x00000505 #define DDRSS_CTL_377_DATA 0x02020200 #define DDRSS_CTL_378_DATA 0x02020202 #define DDRSS_CTL_379_DATA 0x02020202 @@ -403,7 +405,7 @@ #define DDRSS_CTL_389_DATA 0x00000200 #define DDRSS_CTL_390_DATA 0x0000DB60 #define DDRSS_CTL_391_DATA 0x0001E780 -#define DDRSS_CTL_392_DATA 0x0A0B0302 +#define DDRSS_CTL_392_DATA 0x0C0D0302 #define DDRSS_CTL_393_DATA 0x001E090A #define DDRSS_CTL_394_DATA 0x000030C0 #define DDRSS_CTL_395_DATA 0x00000200 @@ -412,7 +414,7 @@ #define DDRSS_CTL_398_DATA 0x00000200 #define DDRSS_CTL_399_DATA 0x0000DB60 #define DDRSS_CTL_400_DATA 0x0001E780 -#define DDRSS_CTL_401_DATA 0x0A0B0302 +#define DDRSS_CTL_401_DATA 0x0C0D0302 #define DDRSS_CTL_402_DATA 0x001E090A #define DDRSS_CTL_403_DATA 0x000030C0 #define DDRSS_CTL_404_DATA 0x00000200 @@ -421,7 +423,7 @@ #define DDRSS_CTL_407_DATA 0x00000200 #define DDRSS_CTL_408_DATA 0x0000DB60 #define DDRSS_CTL_409_DATA 0x0001E780 -#define DDRSS_CTL_410_DATA 0x0A0B0302 +#define DDRSS_CTL_410_DATA 0x0C0D0302 #define DDRSS_CTL_411_DATA 0x0000090A #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -601,14 +603,14 @@ #define DDRSS_PI_164_DATA 0x00007800 #define DDRSS_PI_165_DATA 0x00780078 #define DDRSS_PI_166_DATA 0x00141414 -#define DDRSS_PI_167_DATA 0x00000038 -#define DDRSS_PI_168_DATA 0x00000038 -#define DDRSS_PI_169_DATA 0x00040038 +#define DDRSS_PI_167_DATA 0x0000003A +#define DDRSS_PI_168_DATA 0x0000003A +#define DDRSS_PI_169_DATA 0x0004003A #define DDRSS_PI_170_DATA 0x04000400 #define DDRSS_PI_171_DATA 0xC8040009 -#define DDRSS_PI_172_DATA 0x04000918 -#define DDRSS_PI_173_DATA 0x000918C8 -#define DDRSS_PI_174_DATA 0x0018C804 +#define DDRSS_PI_172_DATA 0x0400091C +#define DDRSS_PI_173_DATA 0x00091CC8 +#define DDRSS_PI_174_DATA 0x001CC804 #define DDRSS_PI_175_DATA 0x00000118 #define DDRSS_PI_176_DATA 0x00001860 #define DDRSS_PI_177_DATA 0x00000118 @@ -621,14 +623,14 @@ #define DDRSS_PI_184_DATA 0x010C010C #define DDRSS_PI_185_DATA 0x0000010C #define DDRSS_PI_186_DATA 0x00000000 -#define DDRSS_PI_187_DATA 0x03000000 -#define DDRSS_PI_188_DATA 0x01010303 +#define DDRSS_PI_187_DATA 0x05000000 +#define DDRSS_PI_188_DATA 0x01010505 #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x00181818 #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 -#define DDRSS_PI_193_DATA 0x0B000000 -#define DDRSS_PI_194_DATA 0x0A0A0B0B +#define DDRSS_PI_193_DATA 0x0D000000 +#define DDRSS_PI_194_DATA 0x0A0A0D0D #define DDRSS_PI_195_DATA 0x0303030A #define DDRSS_PI_196_DATA 0x00000000 #define DDRSS_PI_197_DATA 0x00000000 @@ -656,15 +658,15 @@ #define DDRSS_PI_219_DATA 0x001600C8 #define DDRSS_PI_220_DATA 0x010100C8 #define DDRSS_PI_221_DATA 0x00001B01 -#define DDRSS_PI_222_DATA 0x1F0F0051 -#define DDRSS_PI_223_DATA 0x03000001 -#define DDRSS_PI_224_DATA 0x001B0A0B -#define DDRSS_PI_225_DATA 0x1F0F0051 -#define DDRSS_PI_226_DATA 0x03000001 -#define DDRSS_PI_227_DATA 0x001B0A0B -#define DDRSS_PI_228_DATA 0x1F0F0051 -#define DDRSS_PI_229_DATA 0x03000001 -#define DDRSS_PI_230_DATA 0x00000A0B +#define DDRSS_PI_222_DATA 0x1F0F0053 +#define DDRSS_PI_223_DATA 0x05000001 +#define DDRSS_PI_224_DATA 0x001B0A0D +#define DDRSS_PI_225_DATA 0x1F0F0053 +#define DDRSS_PI_226_DATA 0x05000001 +#define DDRSS_PI_227_DATA 0x001B0A0D +#define DDRSS_PI_228_DATA 0x1F0F0053 +#define DDRSS_PI_229_DATA 0x05000001 +#define DDRSS_PI_230_DATA 0x00010A0D #define DDRSS_PI_231_DATA 0x0C0B0700 #define DDRSS_PI_232_DATA 0x000D0605 #define DDRSS_PI_233_DATA 0x0000C570 @@ -731,52 +733,52 @@ #define DDRSS_PI_294_DATA 0x01000000 #define DDRSS_PI_295_DATA 0x00020201 #define DDRSS_PI_296_DATA 0x00000000 -#define DDRSS_PI_297_DATA 0x00000414 +#define DDRSS_PI_297_DATA 0x00000424 #define DDRSS_PI_298_DATA 0x00000301 #define DDRSS_PI_299_DATA 0x00000000 #define DDRSS_PI_300_DATA 0x00000000 #define DDRSS_PI_301_DATA 0x00000000 -#define DDRSS_PI_302_DATA 0x00000401 +#define DDRSS_PI_302_DATA 0x00001401 #define DDRSS_PI_303_DATA 0x00000493 #define DDRSS_PI_304_DATA 0x00000000 -#define DDRSS_PI_305_DATA 0x00000414 +#define DDRSS_PI_305_DATA 0x00000424 #define DDRSS_PI_306_DATA 0x00000301 #define DDRSS_PI_307_DATA 0x00000000 #define DDRSS_PI_308_DATA 0x00000000 #define DDRSS_PI_309_DATA 0x00000000 -#define DDRSS_PI_310_DATA 0x00000401 +#define DDRSS_PI_310_DATA 0x00001401 #define DDRSS_PI_311_DATA 0x00000493 #define DDRSS_PI_312_DATA 0x00000000 -#define DDRSS_PI_313_DATA 0x00000414 +#define DDRSS_PI_313_DATA 0x00000424 #define DDRSS_PI_314_DATA 0x00000301 #define DDRSS_PI_315_DATA 0x00000000 #define DDRSS_PI_316_DATA 0x00000000 #define DDRSS_PI_317_DATA 0x00000000 -#define DDRSS_PI_318_DATA 0x00000401 +#define DDRSS_PI_318_DATA 0x00001401 #define DDRSS_PI_319_DATA 0x00000493 #define DDRSS_PI_320_DATA 0x00000000 -#define DDRSS_PI_321_DATA 0x00000414 +#define DDRSS_PI_321_DATA 0x00000424 #define DDRSS_PI_322_DATA 0x00000301 #define DDRSS_PI_323_DATA 0x00000000 #define DDRSS_PI_324_DATA 0x00000000 #define DDRSS_PI_325_DATA 0x00000000 -#define DDRSS_PI_326_DATA 0x00000401 +#define DDRSS_PI_326_DATA 0x00001401 #define DDRSS_PI_327_DATA 0x00000493 #define DDRSS_PI_328_DATA 0x00000000 -#define DDRSS_PI_329_DATA 0x00000414 +#define DDRSS_PI_329_DATA 0x00000424 #define DDRSS_PI_330_DATA 0x00000301 #define DDRSS_PI_331_DATA 0x00000000 #define DDRSS_PI_332_DATA 0x00000000 #define DDRSS_PI_333_DATA 0x00000000 -#define DDRSS_PI_334_DATA 0x00000401 +#define DDRSS_PI_334_DATA 0x00001401 #define DDRSS_PI_335_DATA 0x00000493 #define DDRSS_PI_336_DATA 0x00000000 -#define DDRSS_PI_337_DATA 0x00000414 +#define DDRSS_PI_337_DATA 0x00000424 #define DDRSS_PI_338_DATA 0x00000301 #define DDRSS_PI_339_DATA 0x00000000 #define DDRSS_PI_340_DATA 0x00000000 #define DDRSS_PI_341_DATA 0x00000000 -#define DDRSS_PI_342_DATA 0x00000401 +#define DDRSS_PI_342_DATA 0x00001401 #define DDRSS_PI_343_DATA 0x00000493 #define DDRSS_PI_344_DATA 0x00000000 #define DDRSS_PHY_0_DATA 0x04C00000 @@ -871,7 +873,7 @@ #define DDRSS_PHY_89_DATA 0x31804000 #define DDRSS_PHY_90_DATA 0x04BF0340 #define DDRSS_PHY_91_DATA 0x01008080 -#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_92_DATA 0x04050001 #define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E @@ -1127,7 +1129,7 @@ #define DDRSS_PHY_345_DATA 0x31804000 #define DDRSS_PHY_346_DATA 0x04BF0340 #define DDRSS_PHY_347_DATA 0x01008080 -#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_348_DATA 0x04050001 #define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E @@ -2113,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000046 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2184,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x01990000 #define DDRSS_PHY_1403_DATA 0x300D3F11 #define DDRSS_PHY_1404_DATA 0x01990000 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 -- 2.39.5