From e2afbee50c5042fdbca78e2a6f86d9442af68783 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Mon, 10 Aug 2020 10:55:56 +0800 Subject: [PATCH] arm: socfpga: soc64: Document down boot_scratch_cold register usage Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 5e3f54a6a8..4949cae97a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -46,13 +46,21 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 +/* store qspi ref clock */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +/* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +/* store fpga clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +/* reserved for customer use */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 -- 2.39.5