From cb1d68b143afb1129f84c8e3971785e27949fc6b Mon Sep 17 00:00:00 2001 From: Nicolas Heemeryck Date: Mon, 11 Dec 2023 11:06:13 +0100 Subject: [PATCH] clk: imx8mn: add pwm clocks Based on Linux kernel 6.7-rc4, add necessary clocks for the PWM controllers. Signed-off-by: Nicolas Heemeryck Reviewed-by: Fabio Estevam --- drivers/clk/imx/clk-imx8mn.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index 692823e74b..457acb8a40 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -83,6 +83,20 @@ static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_ static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "audio_pll2_out", "sys_pll1_133m", }; +#ifndef CONFIG_SPL_BUILD +static const char *imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; + +static const char *imx8mn_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m", + "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll_out", }; +#endif + static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "m7_alt_pll", "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", }; @@ -330,6 +344,22 @@ static int imx8mn_clk_probe(struct udevice *dev) clk_dm(IMX8MN_CLK_ENET1_ROOT, imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0)); + clk_dm(IMX8MN_CLK_PWM1, + imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380)); + clk_dm(IMX8MN_CLK_PWM2, + imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400)); + clk_dm(IMX8MN_CLK_PWM3, + imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480)); + clk_dm(IMX8MN_CLK_PWM4, + imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500)); + clk_dm(IMX8MN_CLK_PWM1_ROOT, + imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0)); + clk_dm(IMX8MN_CLK_PWM2_ROOT, + imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0)); + clk_dm(IMX8MN_CLK_PWM3_ROOT, + imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0)); + clk_dm(IMX8MN_CLK_PWM4_ROOT, + imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0)); #endif #if CONFIG_IS_ENABLED(DM_SPI) -- 2.39.5