From bfbef68ae1c0386b687e3dbb5043675c501d8714 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Wed, 17 May 2023 13:01:01 +0300 Subject: [PATCH] ARM: dts: rockchip: rock5b: enable pcie2x1l2 and associated combphy Enable the PCIe 2x1l 2 device and associated combphy. On this bus, the Rock5B has an Ethernet transceiver connected. Signed-off-by: Christopher Obbard [eugen.hristev@collabora.com: minor tweaks] Signed-off-by: Eugen Hristev [jonas@kwiboo.se: add PCIe pins] Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index e9fcb7b92e..406303920d 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -30,9 +30,31 @@ }; }; +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &pinctrl { bootph-all; + pcie { + pcie_reset_h: pcie-reset-h { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2x1l2_pins: pcie2x1l2-pins { + rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>, + <3 RK_PD0 4 &pcfg_pull_none>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -- 2.39.5