From bade208b5deb16120c6236e941c6e5f081e86c05 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 31 Oct 2023 00:37:20 -0500 Subject: [PATCH] riscv: Weakly define invalidate_icache_range() Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index c46b49eb0a..afad7e117f 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the -- 2.39.5