From aeaef07c5124afbe848f727a24019cf432f5e011 Mon Sep 17 00:00:00 2001
From: Nicolas Ferre <nicolas.ferre@microchip.com>
Date: Fri, 30 Oct 2020 18:33:14 +0100
Subject: [PATCH] ARM: dts: sama7g5ek: fix TXC pin configuration

TXC line is directly connected from the SoC to the KSZ9131 PHY. There
is a transient state on this signal, before configuring it to RGMII,
which leads to packet transmit being blocked.
Keeping a pull-up when muxing this pin as function A (G0_TXCK) fixes
the issue.

Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
 arch/arm/dts/sama7g5ek.dts | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts
index b7c35559fe..ff9c9eb45c 100644
--- a/arch/arm/dts/sama7g5ek.dts
+++ b/arch/arm/dts/sama7g5ek.dts
@@ -90,7 +90,7 @@
 	#address-cells = <1>;
 	#size-cells = <0>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_gmac0_default>;
+	pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>;
 	phy-mode = "rgmii-id";
 	status = "okay";
 
@@ -173,7 +173,6 @@
 			 <PIN_PA28__G0_RX2>,
 			 <PIN_PA29__G0_RX3>,
 			 <PIN_PA15__G0_TXEN>,
-			 <PIN_PA24__G0_TXCK>,
 			 <PIN_PA30__G0_RXCK>,
 			 <PIN_PA18__G0_RXDV>,
 			 <PIN_PA22__G0_MDC>,
@@ -182,6 +181,11 @@
 		bias-disable;
 	};
 
+	pinctrl_gmac0_txc_default: gmac0_txc_default {
+		pinmux = <PIN_PA24__G0_TXCK>;
+		bias-pull-up;
+	};
+
 	pinctrl_gmac1_default: gmac1_default {
 		pinmux = <PIN_PD30__G1_TXCK>,
 			 <PIN_PD22__G1_TX0>,
-- 
2.39.5