From 9a6569a043d336138fca857bc3140fab33a11afc Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 13 Apr 2023 14:20:08 +0800 Subject: [PATCH] riscv: Update alignment for some sections in linker scripts Some sections in the linker scripts are aligned to 4 bytes, which may cause misaligned exception on some platforms, e.g.: clearing the bss section on 64-bit hardware if __bss_start does not start from a naturally 8 bytes aligned address. Signed-off-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/u-boot-spl.lds | 2 +- arch/riscv/cpu/u-boot.lds | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds index c3b4907905..d1113a59aa 100644 --- a/arch/riscv/cpu/u-boot-spl.lds +++ b/arch/riscv/cpu/u-boot-spl.lds @@ -44,7 +44,7 @@ SECTIONS __binman_sym_end = .; } > .spl_mem - . = ALIGN(4); + . = ALIGN(8); _end = .; _image_binary_end = .; diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 1c937aebee..15b5cbc585 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -57,7 +57,7 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(4); + . = ALIGN(8); /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { @@ -66,7 +66,7 @@ SECTIONS __rel_dyn_end = .; } - . = ALIGN(4); + . = ALIGN(8); .dynsym : { __dyn_sym_start = .; @@ -74,7 +74,7 @@ SECTIONS __dyn_sym_end = .; } - . = ALIGN(4); + . = ALIGN(8); _end = .; -- 2.39.5