From 6c01ca0a530689d45b2ff7d679bd653ad8adaeb4 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 31 Jan 2023 16:42:32 +0800 Subject: [PATCH] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun To resolve DCNANO underrun issue, change the DDR Port 0 arbitration from round robin fashion to fixed priority level 1, while other ports are not assigned any priority, so they will be serviced in round robin fashion if there is no active request from Port 0. Signed-off-by: Ye Li Acked-by: Peng Fan --- board/freescale/imx8ulp_evk/lpddr4_timing.c | 4 ++-- board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c index 1878ca593a..e9edb87128 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0604c8, 0x8000f00 }, /* 306 */ { 0x2e0604cc, 0xa08 }, /* 307 */ { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x102 }, /* 309 */ - { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ { 0x2e0604dc, 0x40400 }, /* 311 */ { 0x2e0604e0, 0x4040000 }, /* 312 */ { 0x2e0604e4, 0x4000000 }, /* 313 */ diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c index e48cb965c1..9728a25441 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c @@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0604c8, 0x8000f00 }, /* 306 */ { 0x2e0604cc, 0xa08 }, /* 307 */ { 0x2e0604d0, 0x1010101 }, /* 308 */ - { 0x2e0604d4, 0x102 }, /* 309 */ - { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604d4, 0x01000102 }, /* 309 */ + { 0x2e0604d8, 0x00000101 }, /* 310 */ { 0x2e0604dc, 0x40400 }, /* 311 */ { 0x2e0604e0, 0x4040000 }, /* 312 */ { 0x2e0604e4, 0x4000000 }, /* 313 */ -- 2.39.5