From 64339bc1f2ae2c0bfcc058a5001284a9a222f15b Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Fri, 25 Aug 2023 00:25:20 +0800 Subject: [PATCH] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT -- 2.39.5