From 4adb16b29a31590f536b72e635370aff73732b4d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Sep 2021 16:11:55 +0200 Subject: [PATCH] phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/phy/marvell/comphy_a3700.c | 2 +- drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 06822d1d12..504f4b2bb1 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16(phy_addr(PCIE, MISC_REG0), - 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 8748c6c84a..23c8ffbff4 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) #define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) +#define rb_txdclk_2x_sel BIT(6) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10) -- 2.39.5