From 39fb8acac42652bf7c1388471b7321e6c6ec1859 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 11 Oct 2023 18:29:44 +0800 Subject: [PATCH] clk: rk3588: Add 742.5M parameter for PLL For a specific frequency. Signed-off-by: Guochun Huang Signed-off-by: Elaine Zhang Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3588.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 119b1337bd..c861762641 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(816000000, 2, 272, 2, 0), RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(742500000, 4, 495, 2, 0), RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), RK3588_PLL_RATE(600000000, 2, 200, 2, 0), RK3588_PLL_RATE(594000000, 2, 198, 2, 0), -- 2.39.5