From 34ae2b2abb950e62e64721b14c6ee8c8794c1ca4 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Apr 2023 14:16:56 +0200 Subject: [PATCH] clk: mpc83xx: Fix clocks for mpc832x gd->arch.sdhc_clk only exists when CONFIG_FSL_ESDHC is set, so enclose it inside ifdefs. gd->arch.qe_clk and gd->arch.brg_clk must be populated when CONFIG_QE is set. Signed-off-by: Christophe Leroy --- drivers/clk/mpc83xx_clk.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c index 0255ccaf8a..cc734450ef 100644 --- a/drivers/clk/mpc83xx_clk.c +++ b/drivers/clk/mpc83xx_clk.c @@ -346,8 +346,10 @@ static int mpc83xx_clk_probe(struct udevice *dev) type = dev_get_driver_data(dev); +#ifdef CONFIG_FSL_ESDHC if (mpc83xx_has_sdhc(type)) gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC]; +#endif gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE]; gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1]; @@ -362,6 +364,11 @@ static int mpc83xx_clk_probe(struct udevice *dev) gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; +#ifdef CONFIG_QE + gd->arch.qe_clk = priv->speed[MPC83XX_CLK_QE]; + gd->arch.brg_clk = priv->speed[MPC83XX_CLK_BRG]; +#endif + return 0; } -- 2.39.5