From 137db2af147979dc27d912e0567e7953a9380df3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Pali=20Roh=C3=A1r?= Date: Tue, 21 Dec 2021 12:20:15 +0100 Subject: [PATCH] pci: pci_mvebu: Remove dependency on SOC_REGS_PHY_BASE macro MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit SoC specific macro SOC_REGS_PHY_BASE is used for two things: * calculation of base PCIe port address * filling PCIe register with address of internal registers For calculating base PCIe port address use function ofnode_translate_address() which translates DT "assigned-addresses" to final PCIe port address. And for calculating address of internal registers use untranslated and translated DT "assigned-addresses". Basically this change reads SOC_REGS_PHY_BASE address indirectly from DT. Signed-off-by: Pali Rohár --- drivers/pci/pci_mvebu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 2e2fa31877..f8a2272a8f 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -67,6 +67,7 @@ struct mvebu_pcie { struct resource mem; void __iomem *iobase; struct resource io; + u32 intregs; u32 port; u32 lane; int devfn; @@ -350,7 +351,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) pcie->base + PCIE_BAR_CTRL_OFF(1)); /* Setup BAR[0] to internal registers. */ - writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); + writel(pcie->intregs, pcie->base + PCIE_BAR_LO_OFF(0)); writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); } @@ -589,7 +590,8 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev) goto err; } - pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE); + pcie->base = (void *)(u32)ofnode_translate_address(dev_ofnode(dev), addr); + pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]); return 0; -- 2.39.5