From 0b93899bfb548a9590cc7723afb97a1f38f5232f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 17 Sep 2023 16:11:29 +0200 Subject: [PATCH] clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3 Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- drivers/clk/renesas/r8a7796-cpg-mssr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 27cf62e021..ea1f6d6906 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -52,7 +52,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7796_core_clks[] = { +static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -128,7 +128,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a7796_mod_clks[] = { +static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), @@ -299,7 +299,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, -- 2.39.5