From 06183ac5f583d6a6279dd5479cd9b44b7edd9d4c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 16 Jan 2021 00:33:17 +0100 Subject: [PATCH] pci: renesas: Fix BAR mapping on Gen3 Because the first PCIExAR(n) register is configured with the mapping, It is the second PCIExAR(n) register that must be written with 0, not the last one. Update the n from 4 to 1 to select the correct register. Signed-off-by: Marek Vasut Cc: Bin Meng Cc: Nobuhiro Iwamatsu --- drivers/pci/pci-rcar-gen3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 6b08409b85..34a561ef8b 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -358,9 +358,9 @@ static int rcar_gen3_pcie_probe(struct udevice *dev) break; } - writel(0, priv->regs + PCIEPRAR(4)); - writel(0, priv->regs + PCIELAR(4)); - writel(0, priv->regs + PCIELAMR(4)); + writel(0, priv->regs + PCIEPRAR(1)); + writel(0, priv->regs + PCIELAR(1)); + writel(0, priv->regs + PCIELAMR(1)); ret = rcar_gen3_pcie_hw_init(dev); if (ret) -- 2.39.5