From 014a31907ad9185510cea645a6b9b49ad177f6ac Mon Sep 17 00:00:00 2001 From: Jon Lin Date: Thu, 27 Apr 2023 10:35:33 +0300 Subject: [PATCH] pci: pcie_dw_rockchip: Support max_link_speed dts property Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- drivers/pci/pcie_dw_rockchip.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 8ef4d6370f..6da618055c 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -42,6 +42,7 @@ struct rk_pcie { struct clk_bulk clks; struct reset_ctl_bulk rsts; struct gpio_desc rst_gpio; + u32 gen; }; /* Parameters for the waiting for iATU enabled routine */ @@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) rk_pcie_writel_apb(priv, 0x0, 0xf00040); pcie_dw_setup_host(&priv->dw); - ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3); + ret = rk_pcie_link_up(priv, priv->gen); if (ret < 0) goto err_link_up; @@ -397,6 +398,9 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) goto rockchip_pcie_parse_dt_err_phy_get_by_index; } + priv->gen = dev_read_u32_default(dev, "max-link-speed", + LINK_SPEED_GEN_3); + return 0; rockchip_pcie_parse_dt_err_phy_get_by_index: -- 2.39.5