]> git.dujemihanovic.xyz Git - u-boot.git/commit
projects / u-boot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: edd9ad8) | patch
riscv: cpu: fu740: clear feature disable CSR
authorGreen Wan <green.wan@sifive.com>
Mon, 3 May 2021 06:23:05 +0000 (23:23 -0700)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 5 May 2021 08:11:27 +0000 (16:11 +0800)
commitbc8bbb77f74f21582b3bfd790334397757f88575
tree4447ce691bef6dd9d3bb165a031d42dfe5e50442tree | snapshot
parentedd9ad81947d2136c71657be88d6cc35a56bd22fcommit | diff
riscv: cpu: fu740: clear feature disable CSR

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/fu540/spl.c diff | blob | history
My U-Boot fork