ram: stm32mp1: protect minimum value in get_bufsize
Add protection on minimum value for result of get_bufsize
and check the alignment of buffer size: only multiple min_size
is allowed; only 4 bytes alignment was checked previously
(value & 0x3).
For example the "Random" test raises an issue when size is not 8 bytes
aligned because address for buffer = address + size / 2 is not word
aligned.
This patch avoid test error for unsupported size value.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Use the define ENV_IS_IN_DEVICE to test if one the
CONFIG_ENV_IS_IN_... is defined and correct the detection of
persistent storage support in the command "env info"
if CONFIG_ENV_IS_NOWHERE is activated.
Since commit 60d5ed2593c9 ("env: allow ENV_IS_NOWHERE with
other storage target") test CONFIG_ENV_IS_NOWHERE is not
enough; see also commit 953db29a1e9c6 ("env: enable saveenv
command when one CONFIG_ENV_IS_IN is activated").
This patch avoids issue for this command in stm32mp1 platform.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 29 Jun 2020 08:34:06 +0000 (10:34 +0200)]
board: st: move type-c stusb1600 controller code in a driver
Migrate the ST Microelectronics STUSB160X Type-C controller code in
a generic I2C driver in st/common, based on Linux one in :
drivers/usb/typec/stusb160x.c
This patch simplifies the stm32mp1 board code and allows to reuse
this STUSB160X driver in other boards.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Tue, 16 Jun 2020 16:27:44 +0000 (18:27 +0200)]
arm: stm32mp: protect DBGMCU_IDC access with BSEC
As debugger must be totally closed on Sec closed chip,
the DBGMCU_IDC register is no more accessible (self
hosted debug is disabled with OTP).
This patch adds a function bsec_dbgswenable() to check
if the DBGMCU registers are available before to access them:
BSEC_DENABLE.DBGSWENABLE = self hosted debug status.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Tue, 16 Jun 2020 16:25:14 +0000 (18:25 +0200)]
arm: stm32mp: stm32prog: add "Device Name" in iproduct during DFU USB enumeration
Add "Device Name" in iproduct during DFU USB enumeration
to have this information in STM32CubeProgrammer trace
(this tools is compatible with @Name since v2.3)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Fabrice Gasnier [Fri, 12 Jun 2020 08:40:58 +0000 (10:40 +0200)]
power: regulator: stm32: vrefbuf: fix a possible overshoot when re-enabling
There maybe an overshoot:
- when disabling, then re-enabling vrefbuf too quickly
- or upon platform reset as external capacitor maybe slow
discharging (VREFBUF is HiZ at reset by default).
VREFBUF is used by ADC/DAC on some boards. An overshoot on the reference
voltage make the conversions inaccurate for a short period of time. So:
- Don't put the VREFBUF in HiZ when disabling, to force an active
discharge.
- Enforce a 1ms OFF/ON delay, also upon reset
Penalty is a 1ms delay is applied (even for a cold boot), when enabling
VREFBUF.
Fixes: 93cf0ae7758d ("power: regulator: Add support for stm32-vrefbuf") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Patrick Delaunay [Thu, 11 Jun 2020 14:51:17 +0000 (16:51 +0200)]
configs: stm32mp1: activate WATCHDOG
As kernel v5.6 have a solution since so we will be able to enable
the watchdog at boot time. It is reloaded by the watchdog
framework (if CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set) and
until the userspace watchdog daemon takes over control.
Need presence of kernel patch 85fdc63fe256 ("drivers: watchdog:
stm32_iwdg: set WDOG_HW_RUNNING at probe") integrated in v5.6-rc1.
This patch revert the previous commit ca351e705a5c ("stm32mp1:
deactivate WATCHDOG in defconfig").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
pinctrl: stm32: add information on pin configuration
Add information on pin configuration used for pinmux command:
- bias configuration for output (disable, pull up, pull down)
- otype for input (open drain or push pull)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
gpio: stmfx: move function to prepare new ops introduction
Move the functions stmfx_pinctrl_set_pupd and stmfx_pinctrl_set_type;
they can be used by the new ops get_dir_flags and set_dir_flags introduced
by next patch.
No functional change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:49 +0000 (12:19 +0200)]
board: stm32mp1: move the function board_debug_uart_init in spl.c
Move the debug function board_debug_uart_init in spl.c
as the debug_uart_init() function is called in arch_cpu_init()
only for SPL and remove the board.c file.
For TFABOOT, the UART TX pin configuration is done in TF-A.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:48 +0000 (12:19 +0200)]
ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:47 +0000 (12:19 +0200)]
board: stm32mp1: update vddcore in SPL
For board using STPMIC1, the vddcore is provided by BUCK1 of STPMIC1
and need to be updated for 800MHz support and only after the clock
tree initialization.
The VDDCORE voltage value is provided by clock driver, saved in global
variable opp_voltage_mv and udpated in SPL board_early_init_f(),
just after clock tree initialization.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:46 +0000 (12:19 +0200)]
board: st: stpmic1: add function stpmic1_init
Add a function stmpic_init to early initialize the PMIC STPMIC1
- keep vdd on during the reset cycle (to avoid issue when backup battery
is absent)
- Check if debug is enabled to program PMIC according to the bit
This patch allows to remove the compilation of spl.c file from stm32mp1
board in dh_stm32mp1.
CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier
in SPL, in the function board_early_init_f.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 25 May 2020 10:19:42 +0000 (12:19 +0200)]
ARM: dts: stm32: add cpufreq support on stm32mp15x
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Thu, 14 May 2020 13:00:23 +0000 (15:00 +0200)]
net: dwc_eth_qos: update the compatible supported for STM32
Update the compatible associated with the STM32 MPU glue
in the DWC ethernet driver.
The supported compatible is the specific "st,stm32mp1-dwmac"
as indicated in Linux binding
Documentation/devicetree/bindings/net/stm32-dwmac.txt
and not the "snps,dwmac-4.20a" only used to the select IP
version.
This glue is implemented in Linux kernel in:
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
For information in stm32mp151.dtsi, the 2 compatibles are
supported:
As part of merging the next branch in to master, the sifive_fu540 will
fail to link:
riscv64-linux-ld.bfd: lib/built-in.o: in function `panic_finish':
lib/panic.c:28: undefined reference to `do_reset'
make[2]: *** [spl/u-boot-spl] Error 1
make[1]: *** [spl/u-boot-spl] Error 2
make: *** [sub-make] Error 2
And while the "fix the build" option of enabling CONFIG_SPL_SYSRESET may
solve the issue, it is unclear that it is the correct path exactly. For
the moment, I am reverting this commit and take a "revert the revert"
and proper fix as soon as it's available.
video: restore CONFIG_VIDCONSOLE_AS_LCD as boolean
This patch restores CONFIG_VIDCONSOLE_AS_LCD as boolean
and introduce a separate sting as CONFIG_VIDCONSOLE_AS_NAME
to search this string in stdout used as videoconsole.
This patch avoid issue with board defconfig or code expecting
CONFIG_VIDCONSOLE_AS_LCD as boolean.
Fixes: 22b897a12323 ("video: extend stdout video console work-around for 'vga'") Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tom Rini [Sun, 5 Jul 2020 22:13:12 +0000 (18:13 -0400)]
Merge tag 'efi-2020-10-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for UEFI sub-system for efi-2020-10-rc1
This series comprises error corrections for the UEFI subsystem:
* correct consideration of timestamps for variable authentication
* correct collection of data regions for code authentication
* correct unit tests to test loading dbx
* enable FAT_WRITE as required by the UEFI spec
The boot manager uses log functions instead of printf() and debug().
Tom Rini [Sun, 5 Jul 2020 22:03:32 +0000 (18:03 -0400)]
Merge branch '2020-07-01-kconfig-etc-updates' into next
- Resync Kconfiglib with the v14.1.0 release.
- Re-sync our <linux/compiler*h> files with v5.7-rc5 from upstream.
- Fully resync checkpatch.pl with v5.7 release.
To safely to all of the above, we have a few bugfixes about functions
that need a 'static inline' but weren't. We also stop setting
CROSS_COMPILE in arch/*/config.mk. Finally, with the above changes
boards can now opt-in to optimizing inlining and we do this for the
socfpga stratix10 platform for space savings.
The UEFI specification requires that when UEFI variables are set using time
based authentication we have to check that unused fields of the timestamp
are zero
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 3 Jul 2020 16:00:36 +0000 (12:00 -0400)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- sbi: Add newline to error message
- fu540: dts: Correct reg size of otp and dmc nodes
- Enhance reserved memory fixup about PMP information passed from OpenSBI
- sifive: fu540: Add gpio-restart support
- qemu-riscv: Update QEMU run command
- Assorted fixes related to reserved memory
- fu540: enable all cache ways from U-Boot proper
- use log functions in fdt_fixup
A time authenticated variable cannot be overwritten with another value
with the same time stamp. So we must ensure the correct sequence of time
stamps when generating out test data.
Using parameter -t for sign-efi-sig-list gives reproducible results and
avoids sleep statements.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
AKASHI Takahiro [Tue, 9 Jun 2020 05:09:31 +0000 (14:09 +0900)]
efi_loader: change efi objects initialization order
The simplest solution to revert the commit b32ac16f9a32 ("test/py: fix
test_efi_secboot/conftest.py") is to move efi_console_register()
forward before efi_disk_register().
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Bin Meng [Tue, 23 Jun 2020 12:23:15 +0000 (05:23 -0700)]
doc: qemu-riscv: Update QEMU run command
Explicitly pass the "-bios" option to QEMU to run U-Boot, instead
of the "-kernel" option, as we know that "-bios" behavior will be
changed since QEMU 5.1.0.
This also updates validated QEMU version to 5.0.0.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
Bin Meng [Fri, 26 Jun 2020 01:16:08 +0000 (18:16 -0700)]
riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the
reserved memory node for PMP protected memory regions. All RISC-V
boards need to copy the reserved memory node from the device tree
provided by the firmware to the device tree used by U-Boot.
Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Fri, 26 Jun 2020 01:16:06 +0000 (18:16 -0700)]
riscv: Avoid the reserved memory fixup if src and dst point to the same place
The copy of reserved memory node from source dtb to destination dtb
can be avoided if they point to the same place. This is useful when
OF_PRIOR_STAGE is used.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
Tom Rini [Tue, 16 Jun 2020 14:29:46 +0000 (10:29 -0400)]
checkpatch.pl: Fully re-sync with v5.7
While commit 048a648298b1 ("checkpatch.pl: Update to v5.7") largely
re-syncs us with checkpatch.pl from v5.7 there are a number of things
missing still. Re-copy the script and again take care to keep our
allowed debug prints and now localized checks intact.
Fixes: 048a648298b1 ("checkpatch.pl: Update to v5.7") Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:09 +0000 (08:30 -0400)]
socfpga: Enable optimized inlining on stratix10
Enable the new CONFIG_OPTIMIZE_INLINING and CONFIG_SPL_OPTIMIZE_INLINING
options for this platform. With gcc-9.2 from kernel.org this saves us
1784 bytes in U-Boot and 80 bytes in SPL.
Cc: Marek Vasut <marex@denx.de> Cc: Chin-Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinh.nguyen@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:07 +0000 (08:30 -0400)]
compiler_types.h: Re-introduce CONFIG_OPTIMIZE_INLINING for U-Boot
In the Linux kernel, support for forcing inline functions to be made
inline, rather than allowing the compiler to make its own choice has
been removed. With respect to performance, modern GCC (and Clang) do a
good job at deciding when to, or not to, inline code and there are no
run-time requirements in Linux anymore.
There is one downside to this, which is final binary size. On average
in U-Boot removing this support grows SPL by almost 1 kilobyte. But
there are cases where it shrinks the binary by making better inline
choices than we had forced.
Start by re-introducing CONFIG_OPTIMIZE_INLINING as a global which
essentially reverts 889b3c1245de ("compiler: remove CONFIG_OPTIMIZE_INLINING entirely")
from Linux.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:06 +0000 (08:30 -0400)]
compiler*.h: sync include/linux/compiler*.h with Linux 5.7-rc5
Copy these from Linux v5.7-rc5 tag.
This brings in some handy new attributes and is otherwise important to
keep in sync.
We drop the reference to smp_read_barrier_depends() as it is not
relevant on the architectures we support at this time, based on where
it's implemented in Linux today. We drop the call to kasan_check_read()
as that is not relevant to U-Boot as well.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:05 +0000 (08:30 -0400)]
socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Thu, 14 May 2020 12:30:04 +0000 (08:30 -0400)]
x86: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.
Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 14 May 2020 12:30:03 +0000 (08:30 -0400)]
tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 14 May 2020 12:30:02 +0000 (08:30 -0400)]
Don't start ad-hoc games with -Wno-maybe-initialized
Borrowing from Linux commit 78a5255ffb6a ("Stop the ad-hoc games with -Wno-maybe-initialized")
move to have maybe-initialized warnings be handled with building with
W=2 instead of playing more guessing games with newer compilers.
Tom Rini [Thu, 14 May 2020 12:30:01 +0000 (08:30 -0400)]
kconfig: Add scripts/Kconfig.include from v4.19
As part of re-syncing our Kconfig logic up to v4.19, we had missed
adding this new file that includes helper macros. To quote the upstream
commit e1cfdc0e72fc ("kconfig: add basic helper macros to scripts/Kconfig.include"):
Kconfig got text processing tools like we see in Make. Add Kconfig
helper macros to scripts/Kconfig.include like we collect Makefile
macros in scripts/Kbuild.include.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 19 May 2020 14:32:33 +0000 (10:32 -0400)]
Remove CROSS_COMPILE default from arch/*/config.mk
In order to support the compiler providing information used within
Kconfig itself we cannot have the compiler be determined by
arch/*/config.mk as we will not be able to evaluate that yet. Given
that most documentation tells people to specify CROSS_COMPILE, remove
these references.
Cc: Huan Wang <alison.wang@nxp.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Michal Simek <monstr@monstr.eu> Cc: Rick Chen <rick@andestech.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Wolfgang Denk <wd@denx.de> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
riscv: cpu: check and append L1 cache to cpu features
All cpu cores within FU540-C000 having split I/D caches.
Set the L1 cache feature bit using the i-cache-size or d-cache-size
as one of the property from device tree indicating that L1 cache is
present on the cpu core.
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit
The conditional check to read "mmu-type" from the device tree
is not rightly handled due to which the cpu feature doesn't include
CPU_FEAT_MMU even if it's corresponding entry is present in the device
tree.
The initialization of cpu features is now taken care in cpu-uclass
driver, so no need to zero out cpu_freq in riscv_cpu driver and can be
removed.
The cmd "cpu detail" fetches uninitialized cpu feature information
and thus displays wrong / inconsitent details as below.
For eg: FU540-C000 doesn't have any microcode, yet the cmd display's it.
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz: L1 cache, MMU, Microcode, Device ID
Microcode version 0x0
Device ID 0x0
The L1 cache or MMU entry seen above is also displayed inconsistently.
So initialize cpu information to zero into cpu-uclass itself so that
similar issues can be avoided for other CPU drivers.
We now see correct features as:
=> cpu detail
1: cpu@1 rv64imafdc
ID = 1, freq = 999.100 MHz
2: cpu@2 rv64imafdc
ID = 2, freq = 999.100 MHz
3: cpu@3 rv64imafdc
ID = 3, freq = 999.100 MHz
4: cpu@4 rv64imafdc
ID = 4, freq = 999.100 MHz
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
0: cpu@4 rv64imafdc
Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding
corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:
=> cpu list
1: cpu@1 rv64imafdc
2: cpu@2 rv64imafdc
3: cpu@3 rv64imafdc
4: cpu@4 rv64imafdc
Sean Anderson [Wed, 24 Jun 2020 10:41:25 +0000 (06:41 -0400)]
riscv: Add Sipeed Maix support
The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.
Documentation for Maix boards is located at
<http://dl.sipeed.com/MAIX/HDK/>. Documentation for the Kendryte K210 is
located at <https://kendryte.com/downloads/>. However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
<https://github.com/kendryte/kendryte-standalone-sdk>.
Sean Anderson [Wed, 24 Jun 2020 10:41:23 +0000 (06:41 -0400)]
riscv: Add device tree for K210 and Sipeed Maix BitM
Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.
Sean Anderson [Wed, 24 Jun 2020 10:41:22 +0000 (06:41 -0400)]
riscv: Enable cpu clock if it is present
The cpu clock is probably already enabled if we are executing code (though
we could be executing from a different core). This patch prevents the cpu
clock or its parents from being disabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:21 +0000 (06:41 -0400)]
riscv: Try to get cpu frequency from a "clocks" node if it exists
Instead of always using the "clock-frequency" property to determine cpu
frequency, try using a clock in "clocks" if it exists. This patch also
fixes a bug where there could be spurious higher frequencies if sizeof(u32)
!= sizeof(ulong).
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:20 +0000 (06:41 -0400)]
riscv: Allow use of reset drivers
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Wed, 24 Jun 2020 10:41:19 +0000 (06:41 -0400)]
riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs. Using the new CSR on an old processor causes an illegal
instruction exception. This patch adds an option to use the old CSRs
instead of the new one.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log
