binman: Convert FIT entry type to a subclass of Section entry type
The binman FIT entry type shares some code with the Section entry type.
This shared code is bound to grow, since FIT entries are conceptually a
variation of Section entries.
Make FIT entry type a subclass of Section entry type, simplifying it a
bit and providing us the features that Section implements. Also fix the
subentry alignment test which now attempts to write symbols to a
nonexistent SPL ELF test file by creating it first.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Avoid AddMissingProperties() and SetCalculatedProperties() with FIT: Signed-off-by: Simon Glass <sjg@chromium.org>
binman: Check missing bintools of Section subclasses
Binman can check for missing binary tools and prints warnings if
anything required for an image is missing. The implementation of this
for the Section entry only checks the subentries, presumably because
Section does not use any binary tools itself. However, this means the
check is also skipped for subclasses of Section which might need binary
tools.
Make sure missing binary tools are checked for subclasses of the Section
entry type as well, by calling the parent class' implementation in
the relevant Section method.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
binman: Register and check bintools from FIT subentries
Binman keeps track of binary tools each entry wants to use. The
implementation of this for the FIT entry only adds "mkimage", but not
the tools that would be used by its subentries.
Register the binary tools that FIT subentries will use in addition to
the one FIT itself uses, and check their existence by copying the
appropriate method from Section entry type. Also add tests that check if
these subentries can use and warn about binary tools.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Binman tries to expand some entries into parts that make it up, e.g.
'u-boot' into a 'u-boot-expanded' section that contains 'u-boot-nodtb'
and 'u-boot-dtb'. Entries with child entries must call ExpandEntries()
on them to build a correct image, as it's possible that unexpanded child
entries have no data of their own. The FIT entry type doesn't currently
do this, which means putting a "u-boot" entry inside it doesn't work as
expected.
Implement ExpandEntries() for FIT and add a copy of a simple FIT image
test that checks subentry expansion in FIT entries.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Moritz Fischer [Sat, 5 Feb 2022 20:17:45 +0000 (12:17 -0800)]
acpi: Move MCFG implementation to common lib
MCFG tables are used on multiple arches. Move to common ACPI lib.
Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Use sizeof(*mcfg) instead of sizeof(*header) Signed-off-by: Simon Glass <sjg@chromium.org>
Moritz Fischer [Sat, 5 Feb 2022 20:17:44 +0000 (12:17 -0800)]
arch: x86: lib: acpi_table: Fix MCFG entries
Commit d953137526cc ("x86: Move SSDT table to a writer function")
introduced a bug where the actual MCFG entries are no longer generated.
Cc: Simon Glass <sjg@chromium.org> Fixes: d953137526cc ("x86: Move SSDT table to a writer function") Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Trying to redefine wchar_t with -fshort-wchar is not necessary
and leads to build failures when compiling against musl.
Cc: Milan P. Stanić <mps@arvanta.net> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Rasmus Villemoes [Mon, 10 Jan 2022 13:34:41 +0000 (14:34 +0100)]
dts: automatically build necessary .dtb files
When building for a custom board, it is quite common to maintain a
private branch which include some defconfig and .dts files. But to
hook up those .dts files requires modifying a file "belonging" to
upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch
to a newer upstream then often results in a conflict which, while it
is trivial to resolve by hand, makes it harder to have a CI do "try to
build our board against latest upstream".
The .config usually includes information on precisely what .dtb(s) are
needed, so to avoid having to modify the Makefile, simply add the
files in (SPL_)OF_LIST to dtb-y.
A technicality is that (SPL_)OF_LIST is not always defined, so rework
the Kconfig symbols so that (SPL_)OF_LIST is always defined (when
(SPL_)OF_CONTROL), but only prompted for in the cases which used to be
their "depends on".
nios2 and microblaze already have something like this in their
dts/Makefile, and the rationale in commit 41f59f68539 is similar to
the above. So this simply generalizes existing practice. Followup
patches could remove the logic in those two makefiles, just as there's
potential for moving some common boilerplate from all the
arch/*/dts/Makefile files to the new scripts/Makefile.dts.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 9 Feb 2022 14:29:07 +0000 (09:29 -0500)]
Merge branch '2022-02-08-Kconfig-updates'
- Assorted general code cleanups to make sure we use the right macros
and use them correctly and buildman updates around kconfig.h itself.
- Convert some IDE and SCSI symbols to Kconfig.
- Convert CONFIG_REMAKE_ELF
- Introduce conversion deadline for DM_SCSI.
Simon Glass [Sat, 22 Jan 2022 12:53:24 +0000 (05:53 -0700)]
Convert CONFIG_SYS_IDE_MAXBUS et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_IDE_MAXBUS
CONFIG_SYS_IDE_MAXDEVICE
CONFIG_SYS_ATA_BASE_ADDR
CONFIG_SYS_ATA_STRIDE
CONFIG_SYS_ATA_DATA_OFFSET
CONFIG_SYS_ATA_REG_OFFSET
CONFIG_SYS_ATA_ALT_OFFSET
CONFIG_SYS_ATA_IDE0_OFFSET
CONFIG_SYS_ATA_IDE1_OFFSET
CONFIG_ATAPI
CONFIG_IDE_RESET
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
Simon Glass [Sat, 22 Jan 2022 12:07:31 +0000 (05:07 -0700)]
buildman: Add helper functions for updating .config files
At present the only straightforward way to write tests that need a
slightly different configuration is to create a new board with its own
configuration. This is cumbersome.
It would be useful if buildman could adjust the configuration of a build
on the fly. In preparation for this, add a utility library which can
modify a .config file according to various parameters passed to it.
Simon Glass [Sat, 22 Jan 2022 12:07:29 +0000 (05:07 -0700)]
buildman: Add a flag to control the traceback
At present the full horror of the Python traceback is shown by default. It
is normally only useful for debugging. Turn it off by default and add a
--debug flag to enable it.
Simon Glass [Sat, 22 Jan 2022 12:07:27 +0000 (05:07 -0700)]
bloblist: Update to use conditional value
Use the new IF_ENABLED_INT() feature to avoid needing our own inline
function to handle this case. Tidy up the logic to ensure that the value
is only used when present. Update the 'expected' comment also.
Add a new IF_ENABLED_INT() to help with this. So now it is possible to
write, without #ifdefs:
static void handle_wibble(void)
{
int val = IF_ENABLED_INT(CONFIG_WIBBLE, CONFIG_WIBBLE_ADDR);
...
}
static void init_machine()
{
...
if (IS_ENABLED(CONFIG_WIBBLE))
handle_wibble();
}
The value will be CONFIG_WIBBLE_ADDR if CONFIG_WIBBLE is defined and will
produce a build error if not.. This allows us to reduce the use of #ifdef
in the code, ensuring that the compiler still checks the code even if it
is not ultimately used for a particular build.
Add a CONFIG_IF_ENABLED_INT() version as well.
If an attempt is made to use a value that does not exist (i.e. when the
conditional is not enabled), an error about a non-existing function is
generated, e.g.:
common/bloblist.c:447: undefined reference to `invalid_use_of_IF_ENABLED_INT'
Simon Glass [Sat, 22 Jan 2022 12:07:25 +0000 (05:07 -0700)]
kconfig: Update IS_ENABLED() internals
The config_enabled() macro currently uses 0 as the default value. Update
it to allow any value, so we can pass it something else, such as a
non-existent function, to produce a build error if it is not defined.
Also tidy up the code style for IS_ENABLED() and drop the unnecessary
brackets (the value is a simple 0 or 1).
phy: cadence: Sierra: Add support for skipping configuration
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:46 +0000 (13:41 +0530)]
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Swapnil Jakhade [Fri, 28 Jan 2022 08:11:40 +0000 (13:41 +0530)]
phy: cadence: Sierra: Prepare driver to add support for multilink configurations
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Add remoteproc resource handling helpers. These functions
are primarily to parse the resource table and to handle
different types of resources. Carveout, devmem, trace &
vring resources are handled.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix redefinition of "struct resource_table" and compile warnings ] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Keerthy [Thu, 27 Jan 2022 12:16:52 +0000 (13:16 +0100)]
arm: mach-omap2: load/start remoteproc IPU1/IPU2
First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.
do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.
Keerthy [Thu, 27 Jan 2022 12:16:51 +0000 (13:16 +0100)]
reset: dra7: Add a reset driver
Add a reset driver to bring IPs out of reset.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: reset_ops structure member "free" has been renamed to "rfree",
use the latter instead] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Bryan Brattlof [Wed, 26 Jan 2022 22:07:33 +0000 (16:07 -0600)]
soc: soc_ti_k3: update j721e revision numbering
There is a 4 bit VARIANT number inside the JTAGID register that TI
increments any time a new variant for a chip is produced. Each
family of TI's SoCs uses a different versioning scheme based off
that VARIANT number.
CC: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.
Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
Add pinctrl macros for J721S2 SoC. These macro definitions are
similar to that of J721E, but adding new definitions to avoid
any naming confusions in the soc dts files.
checkpatch insists the following error exists:
ERROR: Macros with complex values should be enclosed in parentheses
However, we do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
projects / u-boot.git / log
