Bin Meng [Sat, 22 Dec 2018 09:55:49 +0000 (01:55 -0800)]
fs: cbfs: Fix out of bound access during CBFS walking through
The call to file_cbfs_fill_cache() is given with the parameter
'start' pointing to the offset by the CBFS base address, but
with the parameter 'size' that equals to the whole CBFS size.
During CBFS walking through, it checks files one by one and
after it pass over the end of the CBFS which is 4GiB boundary
it tries to check files from address 0 and so on, until the
overall size the codes checked hits to the given 'size'.
Fix this by passing 'start' pointing to the CBFS base address.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
cbfs_fileheader.len indicates the content size of the file in the
cbfs, and it has nothing to do with cbfs_fileheader.offset which
is the starting address of the file in the cbfs.
Remove such check in file_cbfs_next_file(). Before this change
'cbfsinit' failed with 'Bad CBFS file'. After this change all cbfs
commands are working as expected.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
[bmeng: keep the necessary header sanity check] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Dec 2018 03:00:24 +0000 (22:00 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-uniphier
Please pull UniPhier updates v2019.01
- import DIV_ROUND_CLOSEST_ULL macro from Linux
- import improvement and fix of Denali NAND driver from Linux
- add NAND 200MHz clock to clk driver
- allow CONFIG_BOOTCOMMAND to run custom boot command/script
- sync DT with Linux 4.20
This commit improves the ->setup_data_interface() hook.
The denali_setup_data_interface() needs the frequency of clk_x
and the ratio of clk_x / clk.
The latter is currently hardcoded in the driver, like this:
#define DENALI_CLK_X_MULT 6
The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just
chose 6 because it is the most defensive value, but it is not optimal.
By getting the clock rate of both "clk" and "clk_x", the driver can
compute the timing values more precisely.
To not break the existing platforms, the fallback value, 50 MHz is
provided. It is true for all upstreamed platforms.
Currently, denali_dt.c requires a single anonymous clock, but
the Denali User's Guide requires three clocks for this IP:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
This commit supports these named clocks to represent the real hardware.
For the backward compatibility, the driver still accepts a single clock
just as before. The clk_x_rate is taken from the clock driver again if
the named clock "clk_x" is available. This will happen only for future
DT, hence the existing DT files are not affected.
Masahiro Yamada [Wed, 19 Dec 2018 11:03:14 +0000 (20:03 +0900)]
ARM: uniphier: allow to source boot script before distro-boot
Some users might need additional setups before booting the kernel.
If there is found a file 'boot.scr', run it before invoking the
distro boot command.
Lokesh Vutla [Mon, 24 Dec 2018 11:07:41 +0000 (16:37 +0530)]
power: regulator: Return success on attempt to disable an always-on regulator
commit 4f86a724e82c0 ("power: regulator: denied disable on always-on
regulator") throws an error when requested to disable an always-on
regulator. It is right that an always-on regulator should not be
attempted to be disabled. But at the same time regulator framework
should not return an error when such request is received. Instead
it should just return success without attempting to disable the
specified regulator. This is because the requesting driver will
not have the idea if the regulator is always-on or not. The
requesting driver will always try to enable/disable regulator as
per the required flow. So it is upto regulator framework to not
break such scenarios.
Michal Simek [Wed, 19 Dec 2018 15:57:38 +0000 (16:57 +0100)]
phy: Fix u-boot coruption when fixed-phy is used
When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.
The patch is checking if address is in correct range.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Lokesh Vutla [Wed, 19 Dec 2018 07:23:31 +0000 (12:53 +0530)]
arm: K3: Fix usage of CONFIG_SYS_K3_KEY
For signing the tiboot3.bin image, an optional KEY file can be passed
using CONFIG_SYS_K3_KEY. Right now, Makefile scripts directly takes
the config value and uses it for signing. This is okay if the build
directory is a sub-directory of source tree, otherwise it fails.
Fix it by using the path relative to the source tree.
dev_stor_get() is not able to find the next available device in the current
storage group when the previous enumerated device belongs to a different
group or class (e.g. network).
The root cause is the device group iterator not being reset after an
unsuccessful search for the last returned device so that the following
search for the next available device will start from beginning.
The issue has been identified by loading and booting GRUB in a QEMU
vexpress-a9 environment.
Lukasz Majewski [Tue, 18 Dec 2018 11:30:50 +0000 (12:30 +0100)]
dm: pinctrl: Prevent (re-)configuring pins when already done before relocation
This commit prevents from re-configuring pins if those were configured
before relocation.
Some pins - like UART or DDR must be setup before relocation
(as they have 'u-boot,dm-pre-reloc' property set in DTS). Without this
change, those pins are re-configured after relocation (pre_reloc_only = 0,
so we do not "continue").
Such behavior may be a problem for DDR PAD configuration, as they might
be already leveled/tuned with original setup).
Adam Ford [Fri, 14 Dec 2018 22:28:30 +0000 (16:28 -0600)]
ARM: mach-omap2: omap3: Fix GPIO clocking in SPL
OMAP3_GPIO_x is needed to enable each GPIO bank on the OMAP3
boards. At one point, the #ifdef's were replaced with
if CONFIG_IS_ENABLED but this won't work for people who need
OMAP3_GPIO_x in SPL since the SPL prefix for this option isn't
used in Kconfig. This patch moves the check to #if defined and
also makes Kconfig select the banks if CMD_GPIO is used which
makes the checks in the code less cumbersome.
Fixes: bd8a9c14c91c ("arm: mach-omap2/omap3/clock.c: Enable
all GPIO with CMD_GPIO")
Reported-by: Liam O'Shaughnessy <liam.o.shaughnessy@gumstix.com> Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Migrate omap3_igep00x0.h] Signed-off-by: Tom Rini <trini@konsulko.com>
Alexander Graf [Tue, 11 Dec 2018 09:00:42 +0000 (10:00 +0100)]
efi_loader: Make RTS relocation more robust
While changing the RTS alignment to 64KB in commit 7a82c3051c8f
("efi_loader: Align runtime section to 64kb") the relocation code
started to break.
The reason for that is that we didn't actually look at the real
relocation data. We merely took the RUNTIME_CODE section as a
hint and started to relocate based on self calculated data from
that point on. That calculation was now out of sync though.
To ensure we're not running into such a situation again, this patch
makes the runtime relocation code a bit more robust. We can just
trust the phys/virt hints from the payload. We also should check that
we really only have a single section, as the code doesn't handle
multiple code relocations yet.
Fixes: 7a82c3051c8f ("efi_loader: Align runtime section to 64kb") Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reported-by: Loic Devulder <ldevulder@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Tested-by: Loic Devulder <ldevulder@suse.de> Tested-by: Jonathan Gray <jsg@jsg.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
lib: crc32: mark static variable as __efi_runtime_data
In commit 483dbab9f931 ("lib: crc32: mark function crc32() as
__efi_runtime") one local static variable was missed. It did not end up in
the __efi_runtime_data section as it should.
If CONFIG_DYNAMIC_CRC_TABLE=y a data abort execption may occur when the
UEFI payload calls the SetVirtualAddressMap() runtime service.
Reported-by: Dominik Adamski <dominik.adamski@northerntech.community> Fixes: 483dbab9f931 ("lib: crc32: mark function crc32() as __efi_runtime") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Alexander Graf <agraf@suse.de>
Ang, Chee Hong [Thu, 20 Dec 2018 02:35:12 +0000 (18:35 -0800)]
arm: socfpga: stratix10: Add generic FPGA reconfig mailbox API for S10
Add a generic mailbox API for FPGA reconfig status which can be
called by others. This new function accepts 2 different mailbox
commands: CONFIG_STATUS or RECONFIG_STATUS.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Neil Armstrong [Mon, 17 Dec 2018 09:26:16 +0000 (10:26 +0100)]
arm: dts: s400: Fix status for eMMC and SDIO ports
Under U-boot, the WiFi SDIO Module should be disabled and the
eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
include file specific for U-Boot that will be included by the build system.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com>
Paul Burton [Sun, 16 Dec 2018 22:25:23 +0000 (19:25 -0300)]
mips: jz47xx: Add Creator CI20 platform
Add support for the Creator CI20 platform based on the JZ4780 SoC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:22 +0000 (19:25 -0300)]
mips: jz47xx: Add JZ4780 SoC support
Add initial support for the Ingenic JZ47xx MIPS SoC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:21 +0000 (19:25 -0300)]
mips: Add SPL header
Add header with SPL boot mode and type definitions.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Paul Burton [Sun, 16 Dec 2018 22:25:20 +0000 (19:25 -0300)]
mmc: Add JZ47xx SD/MMC controller driver
Add driver for the JZ47xx MSC controller.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
Paul Burton [Sun, 16 Dec 2018 22:25:19 +0000 (19:25 -0300)]
misc: Add JZ47xx efuse driver
Add driver for the efuse block in the JZ47xx SOC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
MIPS: remove local_irq_[save|restore] from CP0 macros
With moving write_on_tlb() to arch/mips/include/asm/mipsregs.h
there are now compiler warnings when some generic code includes
asm/io.h. This happens for example when enabling OF live tree.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Tue, 9 Oct 2018 12:08:42 +0000 (14:08 +0200)]
gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Sat, 8 Dec 2018 08:59:01 +0000 (09:59 +0100)]
pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Gregory CLEMENT [Tue, 9 Oct 2018 12:14:07 +0000 (14:14 +0200)]
DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Stefan Roese [Tue, 18 Dec 2018 09:27:15 +0000 (10:27 +0100)]
mips: mt76xx: linkit/gardena: Don't use CONFIG_OF_EMBED
Building with CONFIG_OF_EMBED generates build warnings, as it should
only be used for debugging purposes. So let's move all MT7688 targets to
CONFIG_OF_SEPARATE instead with this patch.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Tue, 18 Dec 2018 09:27:14 +0000 (10:27 +0100)]
mips: mt76xx: Flush d-cache in arch_misc_init() to solve d-cache issues
It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Remove all interrupt nodes that cause warnings regarding a missing
interrupt parent. There are no interrupt controller nodes defined
and the device trees don't match the ones in Linux anymore.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rick Chen [Tue, 18 Dec 2018 03:02:27 +0000 (11:02 +0800)]
riscv: configs: Rename ax25-ae350 defconfig
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.
Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log
![6 years agoMIPS: remove local_irq_[save|restore] from CP0 macros](/img/sics.gif?p=u-boot.git;a=commit;h=a0abb52c5a5b1de522380984bb9429ee973b1f8e){kind=link}
