This will sort the default environment file generated by
"make u-boot-initial-env", but won't sort the default
environment in the compiled u-boot binary. The file
u-boot-initial-env is considered to use for the userpace
environment access tools [1] in case of that the
environments is written the first time into its location.
This is done on the one hand for a better overview and
comparison of the generated environment file. On the other
hand it is to synchronize the output with the script
get_default_env.sh, which generated a sorted default
environment file. The sorting preserves the order of equal
variable names by sorting only the variable name, and
disable the last-resort comparison. After sorting,
unnoticed blank lines at the end move to the top. Avoid
that by removing it before sorting.
[1] https://github.com/sbabic/libubootenv
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Marek Behún <marek.behun@nic.cz>
To: u-boot@lists.denx.de Reviewed-by: Simon Glass <sjg@chromium.org>
env: Load env when ENV_IS_NOWHERE is only location selected
This patch prevent u-boot from hanging on a UltraZed EG board (zynqmp).
Without the patch,
(drv = env_driver_lookup(ENVOP_INIT, prio))
evaluates to 0, causing prio = 0
Then, (!prio) is hit, returning -ENODEV causing a stall.
With the patch,
instead of returning -ENODEV and causing a stall, we
set gd->env_addr (is this really needed?)
and then
mark gd->env_valid = ENV_INVALID to use the default env.
Fabio Estevam [Sat, 26 Mar 2022 14:47:40 +0000 (11:47 -0300)]
imx8/ls10xx: Use a sane SYS_MALLOC_F_LEN default
When adding new features to imx8m boards, such as DM clock support,
the malloc area can be exhausted.
To avoid such issue, provide a reasonable default for the
SYS_MALLOC_F_LEN size.
Quoting Tom Rini:
"This seems to be an area where everyone is either:
- Kicking the value up a bit for themselves
- Having hard to figure out problems booting the platform because it's
too small a value until they see someone else picked a larger value.
So lets raise these a bit and get some acks, please."
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Fabio Estevam <festevam@denx.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon, imx8mn-beacon Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
This series collects together various misc patches that were needed when
building mainline U-Boot against Chromium OS verified boot. Most of them
fix minor bugs.
Simon Glass [Mon, 28 Feb 2022 19:08:32 +0000 (12:08 -0700)]
stdint: Add a definition of UINT8_MAX
This is normally defined in stdint.h but is not used in U-Boot. When
libraries (such as Chromium OS vboot) are built against U-Boot they may
expect this value to be available. Add it to avoid build errors in this
case.
Simon Glass [Mon, 28 Feb 2022 19:08:22 +0000 (12:08 -0700)]
abuf: Correct a corner case with abuf_realloc()
If the buffer is empty and not allocated, then abuf_realloc() tries to
copy invalid data. This happens because an incorrect change to use
memdup() was added after the original code was written.
Tom Rini [Wed, 6 Apr 2022 15:51:00 +0000 (11:51 -0400)]
Merge branch '2022-04-06-assorted-updates'
- Add DM_PMIC support to TPS65217 and migrate some platforms to it.
- mkimage verification fixes
- DM rST fix, add missing flag when linking u-boot-elf.o
Du Huanpeng [Wed, 30 Mar 2022 18:41:42 +0000 (02:41 +0800)]
Makefile: add endian link flag to u-boot-elf.o
fix compile error when using a little-endian to build with configs:
sfr_nb4-ser_ram_defconfig
comtrend_wap5813n_ram_defconfig
comtrend_ar5387un_ram_defconfig
comtrend_ct5361_ram_defconfig
comtrend_vr3032u_ram_defconfig
comtrend_ar5315u_ram_defconfig
huawei_hg556a_ram_defconfig
netgear_dgnd3700v2_ram_defconfig
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting
fails. The debug UART shows a message
alloc space exhausted
32 is the current maximum number of harts for machine virt in QEMU 7.0.
Raise the default for SYS_MALLOC_F_LEN to 16 KiB.
Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for
other architectures too.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukasz Majewski [Sat, 12 Mar 2022 07:11:10 +0000 (08:11 +0100)]
power: Rename CONFIG_POWER_TPS65217 with CONFIG_PMIC_TPS65217
Up till now the CONFIG_POWER_TPS65217 has been defined in several header
files for am335x SoC.
This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the
role of this IC circuit.
Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig
to be used with boards, which both support DM_PMIC and DM_I2C.
Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Migrate all other platforms as well] Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 5 Apr 2022 15:27:39 +0000 (11:27 -0400)]
Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc1 v2
xilinx:
- Allow booting bigger kernels till 100MB
zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device
serial_zynq:
- Change fifo behavior in DEBUG mode
zynq_sdhci:
- Fix BASECLK setting calculation
clk_zynqmp:
- Add support for showing video clock
gpio:
- Update slg driver to handle DT flags
net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver
pwm:
- Add driver for cadence PWM
versal:
- Add support for reserved memory
firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations
include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers
T Karthik Reddy [Wed, 30 Mar 2022 09:07:56 +0000 (11:07 +0200)]
gpio: slg7xl45106: Update gpio desc flags from DT
In current slg7xl45106 gpio driver xlate() function we are not updating
gpio flags from DT. Read the given flag from DT and update the gpio desc
flags variable with required gpio direction state.
T Karthik Reddy [Wed, 30 Mar 2022 09:07:55 +0000 (11:07 +0200)]
net: zynq_gem: Move ethernet info print statement
As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat
function, phy address always prints as -1. So move the ethernet info
print statement to probe function, to display proper phy address.
T Karthik Reddy [Wed, 30 Mar 2022 09:07:54 +0000 (11:07 +0200)]
net: phy: Avoid phy gpio reset sequence if DM_ETH_PHY is enabled
If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the
eth-phy-uclass driver, so use the PHY gpio reset functionality from
ethernet_id file when this config is disabled to reset the PHY.
Use debug() print instead of dev_err() to avoid warning incase if phy-id
compatible string is not present.
Michal Simek [Wed, 30 Mar 2022 09:07:53 +0000 (11:07 +0200)]
net: zynq_gem: Use shared MDIO bus support for zynqmp
CONFIG_ETH_PHY enables support to utilize generic ethernet phy
framework. Though if ethernet PHY node is in other ethernet node, it
will use shared MDIO to access the PHY of other ethernet.
T Karthik Reddy [Tue, 29 Mar 2022 14:05:57 +0000 (16:05 +0200)]
net: phy: Fix rgmii-id phy reset timeout issue
While creating a phy device using phy_device_create(), we need to
provide a valid phyaddr instead of 0 causing phy address being
registered as 0 with mdio bus and shows mdio phy list as below
ZynqMP> mdio list
eth0:
0 - TI DP83867 <--> ethernet@ff0b0000
eth1:
0 - TI DP83867 <--> ethernet@ff0c0000
Also PHY soft reset is being requested on 0 instead of valid
address causing "PHY reset timed out" error.
So add phyaddr argument to phy_connect_phy_id() and to its prototype
to create phy device with valid phyaddress.
Tom Rini [Tue, 5 Apr 2022 12:33:32 +0000 (08:33 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.
The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
Andre Przywara [Mon, 12 Jul 2021 10:06:51 +0000 (11:06 +0100)]
sunxi: defconfig: enable eMMC boot partition support
Now that the SPL can safely detect whether it was loaded from an eMMC
boot partition or the normal user data partition, let's enable this
feature on some boards that feature eMMC storage.
That covers the boards where I could test this on, and allows the same
build to be written to an SD card, eMMC user partition, eMMC boot
partition, or into SPI NOR flash.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
When the Allwinner BROM loads the SPL from an eMMC boot partition, it
sets the boot source byte to the same value as when booting from the
user data partition. This prevents us from determining the boot source
to load U-Boot proper from the proper partition for sure.
The generic SPL MMC code already looks at the enabled boot partition
number, to load U-Boot proper from the same partition, but this fails
if there is nothing bootable in this partition, as the BROM then
silently falls back to the user data partition, which the SPL misses.
To learn about the actual boot source anyway, we repeat the algorithm
the BROM used to select the boot partition in the first place:
- Test EXT_CSD[179] to check if an eMMC boot partition is enabled.
- Test EXT_CSD[177] to check for valid MMC interface settings.
- Check if BOOT_ACK is enabled.
- Check the beginning of the first sector for a valid eGON signature.
- Load the whole SPL.
- Recalculate the checksum to verify the SPL is valid.
If one of those steps fails, we bail out and continue loading from the
user data partition. Otherwise we load from the selected boot partition.
Since the boot source is needed twice in the boot process, we cache the
result of this test to avoid doing this costly test multiple times.
This allows the very same image file to be put onto an SD card, into the
eMMC user data partition or into the eMMC boot partition, and safely
loads the whole of U-Boot from there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Dave Gerlach [Thu, 17 Mar 2022 17:03:44 +0000 (12:03 -0500)]
board: ti: am64x: Account for DDR size fixups if ECC is enabled
Call into k3-ddrss driver to fixup device tree and resize the available
amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from
R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
this to the OS.
Dave Gerlach [Thu, 17 Mar 2022 17:03:42 +0000 (12:03 -0500)]
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs
The current address being read from dt actually represents the ddrss_ctl
memory region, while ddrss_ss region is something else. Introduce
ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
purpose later so that we can avoid confusion.
Dave Gerlach [Thu, 17 Mar 2022 17:03:40 +0000 (12:03 -0500)]
board: ti: am64x: Use fdt functions for ram and bank init
Use the appropriate fdtdec_setup_mem_size_base and
fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
these values from DT, where they are already available, instead of
hardcoding them.
configs: am64x_evm_a53_defconfig: Switch to per-cpu timer as tick provider
On arm64 systems, recommendation is to use per-cpu timer for time
keeping. Currently AM64 ends up using DM timer as tick timer as driver
is enabled in the config. Drop OMAP DM Timer related configs, this will
switch to using armv8 per-cpu timer as tick timer for A53 SPL/U-Boot.
Hari Nagalla [Wed, 9 Mar 2022 20:42:30 +0000 (14:42 -0600)]
arch: arm: mach-k3: am642_init: Probe ESM nodes
On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high output through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.
Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Hari Nagalla [Wed, 9 Mar 2022 20:42:28 +0000 (14:42 -0600)]
misc: k3_esm: Add functionality to set and route error events within K3SoC
Add functionality to enable, set priority to the input events and to
route to MCU ESM. On AM64x/AM62x devices, it is possible to route Main
ESM0 error events to MCU ESM. When these error events are routed to MCU
ESM high output, it can trigger the reset logic to reset the device,
when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.
K3 based J7 devices (ex: J721e) also have ESM modules, and the changes
to the driver does not impact those devices.
Signed-off-by: Hari Nagalla <hnagalla@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
board: axy17lte: get board usable - add bootcmd and docs
U-boot is intended to replace linux kernel in android boot image(ABL), and
it's FIT payload to replace initramfs file. The boot process is similar to
boot image with linux:
- android bootloader (ABL) unpacks android boot image
- ABL sets `linux,initrd-start property` in chosen node in unpacked FDT
- ABL sets x0 register to FDT address, and passes control to u-boot
- u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable
- u-boot reads `linux,initrd-start` property,
and stores it in `prevbl_initrd_start_addr`
In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env
variable, and boils down to `bootm $prevbl_initrd_start_addr`.
If more control on boot process is desired, pack a boot script in
FIT image, and put it to default configuration
What done:
- Rearrange defconfig option order
- Add CONFIG_SAVE_PREV_BL_* options
- Doc updates:
- remove wrong SBOOT memory corruption note, because
memory is changed during u-boot bringup process,
not by SBOOT
- put payload on ramdisk place in abl boot image
creation step
Andre Przywara [Mon, 12 Jul 2021 10:06:49 +0000 (11:06 +0100)]
spl: mmc: extend spl_mmc_boot_mode() to take mmc argument
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.
Pass the pointer to the mmc struct to that function, so implementations
can make use of that.
Compile-tested for all users changed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA) Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3) Reviewed-by: Simon Glass <sjg@chromium.org>
Jernej Skrabec [Sun, 30 Jan 2022 14:27:13 +0000 (15:27 +0100)]
sunxi: prcm: Add a few registers
H6 and H616 SPL code has a few writes to unknown PRCM registers. Now
that we know what they are, let's replace magic offsets with proper
register names.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 04:52:36 +0000 (23:52 -0500)]
i2c: sun8i_rsb: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
This also has the added benefit of picking the right clock/reset
bits for H6 and new SoCs that have a rearranged PRCM MMIO space.
Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 04:52:35 +0000 (23:52 -0500)]
i2c: sun8i_rsb: Initialize chips in .child_pre_probe
Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case; .probe_chip is only called by dm_i2c_probe, which is
intended for use by board-level code, not for chips with OF nodes.
Since this initialization command must be run before a child chip can be
used, do it before probing each child.
Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 04:52:34 +0000 (23:52 -0500)]
i2c: sun6i_p2wi: Add support for DM clocks and resets
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 04:52:33 +0000 (23:52 -0500)]
i2c: sun6i_p2wi: Initialize chips in .child_pre_probe
Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case; .probe_chip is only called by dm_i2c_probe, which is intended
for use by board-level code, not for chips with OF nodes.
Since this initialization command must be run before a child chip can be
used, do it before probing each child.
Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 05:00:45 +0000 (00:00 -0500)]
sunxi: Support building a SPL as a TOC0 image
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 05:00:44 +0000 (00:00 -0500)]
sunxi: Support SPL in both eGON and TOC0 images
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Fri, 18 Mar 2022 05:00:43 +0000 (00:00 -0500)]
tools: mkimage: Add Allwinner TOC0 support
Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.
A TOC0 image is composed of a header and two or more items. One item
is the firmware binary. The others form a chain linking the firmware
signature to the root-of-trust public key (ROTPK), which has its hash
burned in the SoC's eFuses. Signatures are made using RSA-2048 + SHA256.
The pseudo-ASN.1 structure is manually assembled; this is done to work
around bugs/quirks in the boot ROM, which vary between SoCs. This TOC0
implementation has been verified to work with the A50, A64, H5, H6,
and H616 SBROMs, and it may work with other SoCs.
Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Icenowy Zheng [Fri, 15 Oct 2021 01:53:07 +0000 (20:53 -0500)]
sunxi: specify architecture when generating SPL boot image
As mkimage -T sunxi_egon now gains support for -A parameter, specify the
architecture when generating SPL boot image for sunxi.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Icenowy Zheng [Fri, 15 Oct 2021 01:53:06 +0000 (20:53 -0500)]
mkimage: sunxi_egon: add support for riscv
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Icenowy Zheng [Fri, 15 Oct 2021 01:53:05 +0000 (20:53 -0500)]
mkimage: sunxi_egon: refactor for multi-architecture support
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Icenowy Zheng [Fri, 15 Oct 2021 01:53:04 +0000 (20:53 -0500)]
mkimage: add a flag to describe whether -A is specified
The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.
As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 16:50:28 +0000 (11:50 -0500)]
spi: sun4i_spi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 22:05:35 +0000 (17:05 -0500)]
pinctrl: sunxi: Add SPI0 pinmuxes
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 16:50:51 +0000 (11:50 -0500)]
pwm: sunxi: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 20:52:52 +0000 (15:52 -0500)]
pinctrl: sunxi: Add the A64 PWM pinmux
This is the only possible mux setting for the A64's PWM peripheral.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 16:49:03 +0000 (11:49 -0500)]
sunxi: Remove non-DM MMC pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 21:51:03 +0000 (16:51 -0500)]
pinctrl: sunxi: Add MMC pinmuxes
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Thu, 21 Oct 2021 04:01:29 +0000 (23:01 -0500)]
i2c: sun8i_rsb: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Thu, 21 Oct 2021 04:01:29 +0000 (23:01 -0500)]
i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Thu, 21 Oct 2021 03:55:06 +0000 (22:55 -0500)]
sunxi: Remove options and setup code for I2C2-I2C4
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 20:17:32 +0000 (15:17 -0500)]
pinctrl: sunxi: Add I2C pinmuxes
Where multiple options were available, the one matching board.c and the
device trees was chosen.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fixup H5 I2C1 pinmux] Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 16:49:40 +0000 (11:49 -0500)]
net: sun8i_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 18:34:29 +0000 (13:34 -0500)]
pinctrl: sunxi: Add sun8i EMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 18:16:44 +0000 (13:16 -0500)]
sunxi: Remove non-DM GMAC pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Samuel Holland [Sat, 28 Aug 2021 18:13:52 +0000 (13:13 -0500)]
pinctrl: sunxi: Add sunxi GMAC pinmuxes
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
projects / u-boot.git / log
