rockchip: remove log2 reimplementation from clock drivers
The already available ilog2 function does exactly the same in the common
case than the log2 function the current clock-driver reimplement.
So, simply move to that one.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Kever Yang [Thu, 4 Aug 2016 03:44:58 +0000 (11:44 +0800)]
clock: rk3399: add support for dwmmc 400K
MMC core will use 400KHz for card initialize first and then switch to
higher frequency like 50MHz, we need to support both 400KHz and about
50MHz for dwmmc controller.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
move: rockchip: move clock drivers into a subdirectory
With the number of Rockchip clock drivers increasing, don't clutter up
the core drivers/clk directory with them and instead move them out of
the way into a separate subdirectory.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
Updated for rk3399: Signed-off-by: Simon Glass <sjg@chromium.org>
ARMv8/fsl-ppa: Consolidate PPA image stored-media flag for XIP
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Appended the compatible strings of old version PSCI to the latest
version supported. And there are some psci functions' property must
be added to DT only for psci version 0.1, including cpu_on, cpu_off,
cpu_suspend, migrate.
Note, ARMv8 Secure Firmware Framework doesn't support PSCI ver 0.1.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
York Sun [Fri, 29 Jul 2016 16:02:29 +0000 (09:02 -0700)]
driver/ddr/fsl: Fix timing_cfg_2
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.
Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
Refresh cycle value must be selected based on the frequency
of DDR. tREFI = 7.8 us as per JEDEC. The value for MDREF[REF_CNT]
should be based on round up (tREFI/tCK) formula. For 500MHz, mdref
value should be 0x0f3c8000.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Enable DDR row-bank-column decoding to decode DDR address as
row-bank-column instead of bank-row-column for improving
performance of serial data transfers.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
crypto/fsl: Update blob cmd to accept 64bit addresses
Update blob cmd to accept 64bit source, key modifier and destination
addresses. Also correct output result print format for fsl specific
implementation of blob cmd.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Yunhui Cui [Wed, 13 Jul 2016 02:46:27 +0000 (10:46 +0800)]
driver: spi: fsl-qspi: remove compile Warnings
Warnins log:
drivers/spi/fsl_qspi.c: In function ‘qspi_ahb_read’:
drivers/spi/fsl_qspi.c:400:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Michal Simek [Mon, 1 Aug 2016 06:49:12 +0000 (08:49 +0200)]
ARM64: zynqmp: Do not enable DM_MMC by default
The patch:
"dm: mmc: zynq: Convert zynq to use driver model for MMC"
(sha1: 329a449f2c289b4de8f892fca1d9379ce5fd81b8)
added dependency on enabling some MMC options by default.
There are minimal ZynqMP configurations which require
only minimal configurations to be enabled to keep u-boot size
as lower as possible.
Move options to defconfig instead.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 29 Jul 2016 11:03:29 +0000 (13:03 +0200)]
ARM64: zynqmp: Add u-boot,dm-pre-reloc to clk nodes
Serial driver is getting clk information via DT that's why
also clk node needs to have this flag.
Different behavior was introduced by:
"dm: Use dm_scan_fdt_dev() directly where possible"
(sha1: 911954859d6dece49c3e4835faea004cfe392506)
where simple-bus driver starts to call dm_scan_fdt_dev() which has
additional logic around pre_reloc_only parameter which exclude
clk nodes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 28 Jul 2016 02:33:06 +0000 (20:33 -0600)]
buildman: Add a quick-start note
For those who just want to build a board, it is useful to see a quick hint
right at the start of the documentation. Add a few commands showing how to
download toolchains and build a board.
The current code for setting up the toolchain config always writes the new
paths to an item called 'toolchain'. This means that it will overwrite any
existing toolchain item with the same name. In practice, this means that:
buildman --fetch-arch all
will fetch all toolchains, but only the path of the final one will be added
to the config. This normally works out OK, since most toolchains are the
same version (e.g. gcc 4.9) and will be found on the same path. But it is
not correct and toolchains for archs which don't use the same version will
not function as expected.
Adjust the code to use a complete glob of the toolchain path.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 28 Jul 2016 02:33:04 +0000 (20:33 -0600)]
buildman: Drop the toolchain error when downloading toolchains
It doesn't make sense to complain about missing toolchains when the
--fetch-arch option is being used. The user is presumably aware that there
is a toolchain problem and is actively correcting it by running with this
option.
Refactor the code to avoid printing this confusing message.
Simon Glass [Thu, 28 Jul 2016 02:33:02 +0000 (20:33 -0600)]
buildman: Improve the toolchain progress/error output
Use colour to make it easier to see what is going on. Also print a message
before downloading a new toolchain. Mention --fetch-arch in the message that
is shown when there are no available toolchains, since this is the quickest
way to resolve the problem.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Thu, 28 Jul 2016 02:32:59 +0000 (20:32 -0600)]
buildman: Automatically create a config file if needed
If there is no ~/.buildman file, buildman currently complains and exists. To
make things a little more friendly, create an empty one automatically. This
will not allow things to be built, but --fetch-arch can be used to handle
that.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Thu, 28 Jul 2016 07:06:41 +0000 (09:06 +0200)]
libfdt: Introduce new ARCH_FIXUP_FDT option
Add new Kconfig option to disable arch_fixup_fdt() calls for cases where
U-Boot shouldn't update memory setup in DTB file.
One example of usage of this option is to boot OS with different memory
setup than U-Boot use.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
Hans de Goede [Fri, 29 Jul 2016 09:47:03 +0000 (11:47 +0200)]
sunxi: On newer SoCs use words 1-3 instead of just word 3 from the SID
It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,
This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.
Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 27 Jul 2016 15:58:06 +0000 (17:58 +0200)]
sunxi: Ensure that the NIC specific bytes of the mac are not all 0
On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.
This commits adds a check to ensure this does not happen.
Cc: Chen-Yu Tsai <wens@csie.org> Cc: Corentin LABBE <clabbe.montjoie@gmail.com> Cc: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
sunxi: Hummingbird_A31_defconfig: Drop MACPWR option
MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi: gpio: Add .xlate function for gpio phandle resolution
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.
Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.
Fixes: 7aa974858422 ("dm: sunxi: Modify the GPIO driver to support driver
model") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has
many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and
Gigabit Ethernet.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
rockchip: add basic support for fennec-rk3288 board
Fennec is a RK3288-based development board with 2 USB ports, HDMI,
micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes
on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access
to display pins, I2C, SPI, UART and GPIOs.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
John Keeping [Mon, 25 Jul 2016 09:02:05 +0000 (10:02 +0100)]
rockchip: rk3288: Fix pinctrl for GPIO bank 0
Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers
rather than the GRF registers. In the GRF the top half of the register
is used as a mask so that some bits can be updated without affecting the
others, but in the PMU this feature is not provided and the top half of
the register is reserved.
Take the same approach as the Linux driver to update the value via
read-modify-write but setting the mask for only the bits that have
changed. The PMU registers ignore the top 16 bits so this works for
both GRF and PMU iomux registers.
Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.
Linux format has been respected, as
- max line width at 80 columns
- one 8 cols tab between asm instructions and operands
- inline comments, where any, fixed at col 41
Vignesh R [Fri, 29 Jul 2016 08:52:30 +0000 (14:22 +0530)]
ARM: am57xx_evm: Enable QSPI support
AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Fri, 29 Jul 2016 08:52:31 +0000 (14:22 +0530)]
ARM: dts: am57xx-idk-common: Enable support for QSPI
AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Mon, 25 Jul 2016 10:15:47 +0000 (15:45 +0530)]
ARM: dts: dra7xx: Update spi-max-frequency for QSPI
According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Mon, 25 Jul 2016 10:15:46 +0000 (15:45 +0530)]
configs: dra7xx: Update QSPI speed to 76.8MHz
Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Mon, 25 Jul 2016 10:15:45 +0000 (15:45 +0530)]
spi: ti_qspi: dra7xx: Add support to use 76.8MHz clock
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
Vignesh R [Fri, 22 Jul 2016 05:25:50 +0000 (10:55 +0530)]
spi: ti_qspi: Remove delay in read path for dra7xx
As per commit b545a98f5dc563 ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Fri, 22 Jul 2016 05:25:49 +0000 (10:55 +0530)]
spi: ti_qspi: Fix compiler warning when DEBUG macro is set
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Vignesh R [Fri, 22 Jul 2016 05:25:48 +0000 (10:55 +0530)]
spi: ti_qspi: Fix failure on multiple READ_ID cmd
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Stefan Agner [Tue, 26 Jul 2016 05:57:47 +0000 (22:57 -0700)]
mx7_common: initialize generic timer on all CPU's
Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Stefan Agner [Thu, 21 Jul 2016 04:27:49 +0000 (21:27 -0700)]
colibri_imx7: add Colibri iMX7S/iMX7D module support
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tim Harvey [Fri, 15 Jul 2016 14:16:29 +0000 (07:16 -0700)]
imx: ventana: add dt fixup for watchdog external reset
Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.
This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.
Tim Harvey [Fri, 15 Jul 2016 14:16:28 +0000 (07:16 -0700)]
imx: ventana: refactor board-specific dt fixups (no functional change)
Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
- use defines for DT paths
- use switch/case per board
- order models numerically
Tim Harvey [Fri, 15 Jul 2016 14:14:25 +0000 (07:14 -0700)]
imx: ventana: make hwconfig initialize based on board configuration
The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.
We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.
projects / u-boot.git / log
