Heiko Schocher [Tue, 27 Jun 2017 14:49:14 +0000 (16:49 +0200)]
powerpc: remove 4xx support
There was for long time no activity in the 4xx area.
We need to go further and convert to Kconfig, but it
turned out, nobody is interested anymore in 4xx,
so remove it.
Christophe Leroy [Tue, 27 Jun 2017 14:00:24 +0000 (16:00 +0200)]
doc: restore doc/README.fsl-clk
doc/README.fsl-clk was removed in commit 5b8e76c35ec31 ("powerpc, 8xx: remove support for 8xx")
allthought CONFIG_SYS_FSL_CLK is defined in
arch/arm/cpu/armv8/fsl-layerscape/Kconfig and still in use
in the following configs:
Marek Vasut [Tue, 2 May 2017 18:27:48 +0000 (20:27 +0200)]
ARM: at91: ma5d4: Switch environment start to eMMC
The redesigned version of the SoM which was released onto the market
does no longer contain SPI flash, but boots from the eMMC. Move the
environment storage to the eMMC.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Tue, 2 May 2017 18:27:47 +0000 (20:27 +0200)]
ARM: at91: ma5d4: Boot from MMC2 when using SAM-BA
Continue loading U-Boot from MMC2 when the SPL was loaded using SAM-BA
loader. This allows the board to boot system from the removable media
instead of the eMMC, which is useful for commissioning purposes. When
booting from the eMMC, always boot from it as it is not possible to
boot from the SD interface directly.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Tue, 2 May 2017 18:27:45 +0000 (20:27 +0200)]
ARM: at91: ma5d4: Swap SD/MMC controller order
The SDHCI1 is the primary boot controller on rev. 2.1 SoM, which
is the version available on the market. Swap the controller order
to match this and future versions of the SoM.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Tue, 2 May 2017 18:27:42 +0000 (20:27 +0200)]
ARM: at91: ma5d4: Reset CAN controllers late
The CAN controllers need slight delay between toggling of their reset
line. Move this action into board_init(), otherwise timer will not be
initialized and the board might hang.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Marek Vasut [Tue, 2 May 2017 18:27:41 +0000 (20:27 +0200)]
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com>
Alexey Brodkin [Fri, 25 Nov 2016 13:23:43 +0000 (16:23 +0300)]
arc: Add support for HS Development Kit board
ARC HS Development Kit board is a new low-cost
development platform sporting ARC HS38 in real silicon
with nice set of features such as:
* Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz
* 4Gb of DDR (we use only lowest 1Gb out of it now)
* Lots of DesigWare peripherals
* Different connectivity modules:
- Synopsys HAPS HT3
- Arduino-compatible connector
- MikroBUS
This initial commit supports the following peripherals:
* UART (DW 8250)
* Ethernet (DW GMAC)
* SD/MMC (DW Mobile Storage)
* USB 1.1 & 2.0
Alexey Brodkin [Mon, 26 Jun 2017 08:46:47 +0000 (11:46 +0300)]
arcv2: Set IOC aperture so it covers available DDR
We used to use the same memory layout and size for a couple of
boards and thus we just hardcoding IOC aperture start and size.
Now when we're getting more boards with more memory on board we
need to have an ability to set IOC so it matches real DDR layout
and size.
Even though it is not really a must but for simplicity we assume
IOC covers all the DDR we have, that gives us a chance to not
bother where DMA buffers are allocated - any part of DDR is OK.
Alexey Brodkin [Thu, 1 Jun 2017 14:09:38 +0000 (17:09 +0300)]
axs10x: Move environment from I2C EEPROM to SD-card
With deprecation of I2C EEPROM we we left without a permamnent
storage for U-Boot environment, but luckily we may simply use SD-card
with FAT partition for that.
Having environment on SD-card is much more convenient as it
allows us to preserve all the settings when moving from one board to
another. Moreover instead of 256 bytes of EEPROM we're now virtually
unlimited in stuff being placed in environment like complicated scripts
etc which are usually required in case of full-scale distros.
Alexey Brodkin [Thu, 1 Jun 2017 13:27:27 +0000 (16:27 +0300)]
axs10x: Get rid of both I2C and EEPROM who used to use I2C
With eb5ba3aefdf0 "i2c: Drop use of CONFIG_I2C_HARD" in place we
cannot use I2C EEPROM any longer so we're dropping all references to
both EEPROM and I2C which was only used for EEPROM.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
ARCompact cores are not supposed to be used in SMP designs
(this doesn't stop people from creation of heterogeneous chips,
for an example keep reading) so there's no point in
checking ARCNUM and halting somebody if we build for ARC700.
Moreover on AXS101 board we have ARC770 in the ASIC together with
other ARC cores and ARC770 happens to be the last node in JTAG chain
with ARCNUM = 4. And existing check halts the one and only core we
want keep running.
Heiko Schocher [Fri, 23 Jun 2017 18:13:58 +0000 (20:13 +0200)]
drivers, usb, gadget: fix compiler warnings for at91_udc.c
fix warnings:
drivers/usb/gadget/at91_udc.c:1344:12: warning: 'at91rm9200_udc_init' defined but not used [-Wunused-function]
drivers/usb/gadget/at91_udc.c:1379:13: warning: 'at91rm9200_udc_pullup' defined but not used [-Wunused-function]
drivers/usb/gadget/at91_udc.c:1476:12: warning: 'at91sam9263_udc_init' defined but not used [-Wunused-function]
Bin Meng [Thu, 29 Jun 2017 03:36:25 +0000 (11:36 +0800)]
scripts: config_whitelist: Handle lines with leading spaces/tabs
Some Kconfig options are defined in a line with leading spaces/tabs.
Update build-whitelist/check-config scripts to handle such cases.
Generate a new config_whitelist.txt with new scripts.
Andy Yan [Wed, 28 Jun 2017 08:27:37 +0000 (16:27 +0800)]
ARM: make memset and memcpy prompt message more clearly
The origin SPL_USE_ARCH_MEMSET/MEMCPY use same prompt message
as USE_ARCH_MEMSET/MEMCPY, which makes it's hard to distinguish
them in menuconfig interface. This patch gives them different
prompt messages for spl and none-spl config.
Lukasz Majewski [Mon, 26 Jun 2017 11:04:58 +0000 (13:04 +0200)]
usb: gadget: Call g_dnl_bind_fixup() before testing g_dnl_serial length
After the commit SHA1: 842778a091 - the serial number descriptor is only
visible when we have non zero length of g_dnl_serial.
However, on some platforms (e.g. Siemens) the serial number is set at
g_dnl_bind_fixup(), so with the current code we will always omit the
serial (since it is not set).
This commit moves the g_dnl_bind_fixup() call before the g_dnl_serial
length test.
Tom Rini [Wed, 10 May 2017 16:01:02 +0000 (12:01 -0400)]
ti816x: Enable ethernet support
The ti816x SoC revision of the ethernet IP block is handled by the
"davinci_emac" driver, rather than the "cpsw" driver as done by later
members of the family. Enable the relevant plumbing.
Kever Yang [Tue, 13 Jun 2017 02:03:11 +0000 (10:03 +0800)]
rockchip: clk: rk3036: correct setting for pll integer mode
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 14 Jun 2017 06:54:20 +0000 (14:54 +0800)]
rockchip: mkimage: correct spl_size for rk3399
The maximum spl_size for rk3399 is the internal memory size minus
the size used in bootrom (which usually can get from SPL_TEXT_BASE).
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Wed, 14 Jun 2017 08:14:18 +0000 (16:14 +0800)]
rockchip: rk3399: correct SPL_MAX_SIZE
The SPL_MAX_SIZE is the internal memory size minux the space
used by bootrom.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tom Rini [Fri, 9 Jun 2017 02:33:25 +0000 (22:33 -0400)]
rkcommon.c: Remove unused rkcommon_spi_to_offset
This function is unused, remove. Reported by clang-3.8.
Fixes: a1c29d4b43dc ("rockchip: mkimage: set init_boot_size to avoid ...") Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rob Clark [Tue, 20 Jun 2017 21:55:24 +0000 (17:55 -0400)]
board/db410c: add missing linker map entries for efi
Otherwise the loaded image would miss the efi_runtime sections, and fall
over hard when grub (for example) tried to call runtime services located
in this section.
modified onenand_block_markbad to call mtd_block_markbad,
but as _block_markbad function pointer used by mtd_block_markbad
to do actual job is by default pointing back to
onenand_block_markbad there is no way this function ever
finishes its job.
Fix it by changing function body according current (4.12-rc6)
linux implementation.
Tested on IGEPv2 board with Muxed OneNAND(DDP) 512MB containing
several unerasable blocks this function marked bad.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Ladislav Michl [Tue, 20 Jun 2017 09:44:29 +0000 (11:44 +0200)]
onenand_spl_simple: Add DDP OneNAND support
Current implementation is unable to access second half of
DDP OneNAND flash (reads first half mirrored). Use block
and bufferram address calculations from onenand_base to
fix this.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tom Rini [Fri, 16 Jun 2017 17:06:28 +0000 (13:06 -0400)]
clk_rv1108.c: Fix unused variable warning
The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.
Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
On the controlcenterd_36BIT_SDCARD config we get a warning about
prg_stage1_prepare being unused. Move the declaration closer to usage
and hide under the existing #if tests.
Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Tom Rini <trini@konsulko.com>
It has been observed that between PG1.0 and PG2.0/2.1 depending on
which device we boot from, we may see a different value here than is
documented in the TRM. Update the values for NAND and MMC1 based on
real life usage on each revision.
Ken Ma [Thu, 22 Jun 2017 09:13:36 +0000 (17:13 +0800)]
pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id
In armada_37xx_gpiochip_register, the return value of fdtdec_get_bool
should be true when gpio-controller is found; current codes makes a
wrong inverse return value judgement, this patch fixes it.
Signed-off-by: Ken Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Thu, 22 Jun 2017 09:13:35 +0000 (17:13 +0800)]
pinctrl: a3700: Fix uart2 group selection register mask
If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.
Signed-off-by: Ken Ma <make@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Bin Meng [Thu, 22 Jun 2017 06:42:40 +0000 (14:42 +0800)]
x86: Remove CONFIG_USB_MAX_CONTROLLER_COUNT
As all x86 boards have been switched over to use DM USB, remove
CONFIG_USB_MAX_CONTROLLER_COUNT which is not used by DM USB.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
Bin Meng [Fri, 16 Jun 2017 13:31:46 +0000 (06:31 -0700)]
x86: minnowmax: Configure GPIO pins to turn on USB ports VBUS
GPIO bank E pin 8 & 9 are used to control the on-board two USB ports
VBUS on/off. Let's configure them in the misc_init_r().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 21 Jun 2017 11:54:46 +0000 (07:54 -0400)]
sunxi: Correct select's of SPL_STACK_R and SPL_SYS_MALLOC_SIMPLE
On ARCH_SUNXI we've been selecting these targets for a long time if
SUPPORT_SPL is set. However, Lichee Pi Zero is the first platform we've
added that does support SPL but does not build SPL and has exposed a
latent bug. Both of these symbols depend on SPL not SUPPORT_SPL, so we
need to update our select here otherwise we get a Kconfig warning.
Fixes: f02abb0608fe ("sunxi: add support for Lichee Pi Zero") Signed-off-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Tue, 20 Jun 2017 13:17:19 +0000 (15:17 +0200)]
ARM: rmobile: Add missing config bits
The commit "fb82fe385173 configs: Resync defconfigs" resynced all config
files. This exposed two latent issues with the Gen3 boards in that we
had not been setting CONFIG_DEFAULT_FDT_FILE correctly and had not been
setting CONFIG_CMD_MMC. Fix both of these.
Fixes: fb82fe385173 ("configs: Resync defconfigs") Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Tom Rini <trini@konsulko.com>
Emmanuel Vadot [Tue, 20 Jun 2017 07:02:29 +0000 (09:02 +0200)]
bch: Fix build on FreeBSD host
endian.h on FreeBSD system exist in sys/ subdirectory.
FreeBSD already have a fls function defined in strings.h which is included
in string.h if __BSD_VISIBLE is defined, as a check for this.
Simon Glass [Thu, 8 Jun 2017 03:11:48 +0000 (21:11 -0600)]
tegra: mmc: Set the bus width correctly
The driver currently does not reset bit 5 of the hostctl register even if
the MMC stack requests it. Then means that once a bus width of 8 is
selected it is not possible to change it back to 1. This breaks
'mmc rescan' which needs to start off with a bus width of 1.
The problem was surfaced by enabling CONFIG_DM_MMC_OPS on tegra. Without
this option the MMC stack fully reinits the driver on a 'mmc rescan'.
But with this option driver model does not re-probe a driver once it has
been probed once.
Fix the driver to honour the request.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Chubb <peter.chubb@data61.csiro.au> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Michal Simek [Tue, 7 Feb 2017 13:32:26 +0000 (14:32 +0100)]
arm64: zynqmp: Check pmufw version
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Define routines for mmio write and read
Define routines of mmio write and read functionalities
for zynqmp platform.
Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.
Also make invoke_smc as global so that it can be reused in
multile places where ever possible.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm: zynq: Add Kconfig option for any DDR specific initialization
Add Kconfig option for ddr init as this might be required
in cases like ddr less systems where we want to skip ddrc
init and this option is useful for it.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Mar 2017 10:02:55 +0000 (11:02 +0100)]
arm64: zynqmp: Add comment about level shifter mode v1
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 25 May 2017 14:08:43 +0000 (16:08 +0200)]
arm64: zynqmp: Add empty sleep.h file for psu_init* compilation
psu_init* contain sleep.h header which is not present in u-boot.
Instead of keep comment sleep.h in psu_init* it is easier to add empty
file which is included.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 14 Oct 2016 12:06:28 +0000 (14:06 +0200)]
arm64: zynqmp: Decrease MALLOC size for SPL
Decrease malloc size to 1MB from 256MB. Huge malloc
space is adding huge delay in mem_malloc_init() because
we are enabling CONFIG_SYS_MALLOC_CLEAR_ON_INIT
which clear the whole malloc space.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: spl: fix dual SD controller support
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.
The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c
So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.
Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Feb 2017 07:22:04 +0000 (08:22 +0100)]
microblaze: Build only DTBs for selected target
Adding more targets to repository requires some additional
changes not simply just adding config file, defconfig and dts.
This patch makes this process easier by building only
particular DTB which is selected via defconfig
that Makefile doesn't need to contain all dts files in the repository.
Reported-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 3 May 2017 14:22:30 +0000 (16:22 +0200)]
arm64: zynqmp: Remove CPU_RELEASE_ADDR macro
CPU_RELEASE_ADDR is used only when CONFIG_ARMV8_MULTIENTRY
is enabled. ZynqMP is running ATF which takes care about this
that's why no need to have this macro.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / u-boot.git / log
