Jagan Teki [Wed, 27 Feb 2019 14:32:10 +0000 (20:02 +0530)]
spi: sun4i: Add CLK support
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.
So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.
This patch would also do that change, by enable and disable clock in
proper order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:09 +0000 (20:02 +0530)]
spi: sun4i: Support fifo_depth via drvdata
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:08 +0000 (20:02 +0530)]
spi: sun4i: Access registers and bits via enum offsets
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.
Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.
Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
Jagan Teki [Wed, 27 Feb 2019 14:32:06 +0000 (20:02 +0530)]
clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:05 +0000 (20:02 +0530)]
spi: sun4i: Poll for rxfifo to be filled up
To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.
To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.
So, add code for polling rxfifo to be filled up using fifo
status register.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.
The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
To find out how big the early malloc heap must be in SPL, add a debug
print statement that dumps its usage before switching to relocated heap
in spl_relocate_stack_gd() via CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Stephen Warren [Tue, 26 Feb 2019 19:20:26 +0000 (12:20 -0700)]
kbuild: fix DTB .cmd source variable
*.dts are processed using a custom command, then the C pre-processor is
run on them, then they are compiled using dtc. Thus, the dependency
files generated by both cpp and dtc reference a temporary file name
rather than the actual source file. While this information isn't used
for any purpose by the build system, and hence this causes no functional
issue, it does cause the dependency files to contain invalid and
confusing data, which is unhelpful while debugging build problems. Fix
this using sed.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Stephen Warren [Tue, 26 Feb 2019 19:20:25 +0000 (12:20 -0700)]
kbuild: make arch-dtbs target PHONY
Without this, the arch-dtbs target only gets evaluated when building
U-Boot the first time, not when re-building (incrementally building)
U-Boot. Thus incremental builds ignore changes to DTB files.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Patrick Delaunay [Tue, 26 Feb 2019 12:09:00 +0000 (13:09 +0100)]
doc: binding: rename directory ram to memory-controller
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller
PS: the drivers using RAM u-class should be associated with
this binding directory
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Marek Vasut [Tue, 19 Feb 2019 00:43:51 +0000 (01:43 +0100)]
ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
David Rivshin [Mon, 18 Feb 2019 23:04:29 +0000 (18:04 -0500)]
spi: omap3: fix set_wordlen() reading from incorrect address for CHCONF
_omap3_spi_set_wordlen() indexed the regs->channel[] array with the
old wordlen (instead of the chipselect number) when reading the current
CHCONF register value. This meant it read from the wrong memory location,
modified that value, and then wrote it back to the correct CHCONF
register. The end result is that most slave configuration settings would
be lost, such as clock divisor, clock/chipselect polarities, etc.
Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
Anup Patel [Mon, 25 Feb 2019 08:15:33 +0000 (08:15 +0000)]
riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
because bootm will update initrd location in DTB only if
CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
this option then bootm assumes DTB already has initrd details
which is not the case most of the time.
Atish Patra [Mon, 25 Feb 2019 08:15:27 +0000 (08:15 +0000)]
doc: Add a readme guide for SiFive FU540
The readme guide describes the procedure to build, flash and boot Linux
using U-Boot on HiFive Unleashed. It also explains the current state of
U-boot support and future action items.
Anup Patel [Mon, 25 Feb 2019 08:15:19 +0000 (08:15 +0000)]
riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.
Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Atish Patra [Mon, 25 Feb 2019 08:15:14 +0000 (08:15 +0000)]
cpu: Bind timer driver for boot hart
Currently, timer driver is bound only for hart0.
There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.
The timer driver should be bound for boot hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Anup Patel [Mon, 25 Feb 2019 08:14:49 +0000 (08:14 +0000)]
clk: Add SiFive FU540 PRCI clock driver
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Anup Patel [Mon, 25 Feb 2019 08:14:30 +0000 (08:14 +0000)]
riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.
To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.
Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Anup Patel [Mon, 25 Feb 2019 08:14:24 +0000 (08:14 +0000)]
riscv: Add place-holder asm/arch/clk.h for driver compilation
Some of the drivers (such as Cadence MACB ethernet driver) expect
asm/arch/clk.h to be provided by arch support so we add place-holder
asm/arch-generic/clk.h for RISC-V generic CPU.
Anup Patel [Mon, 25 Feb 2019 08:14:10 +0000 (08:14 +0000)]
riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.
This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.
Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 26 Feb 2019 13:45:08 +0000 (08:45 -0500)]
Merge tag 'efi-2019-04-rc3' of https://github.com/xypron2/u-boot
Pull request for the UEFI sub-system for v2019.04-rc3
A new option -e is added to the env command which allows to display and
change UEFI variables in a user friendly way.
A new command efidebug is introduced to edit the UEFI boot sequence and to
display different aspects of the state of the UEFI sub-system: memory map,
loaded images, handles, drivers and devices.
Marek Vasut [Tue, 19 Feb 2019 18:32:28 +0000 (19:32 +0100)]
mmc: renesas: Unconditionally set DTCNTL TAPNUM to 8
According to latest specification rev.0026 and after confirmation with
HW engineer, the DTCNTL register TAPNUM field must be set to 8 even on
H3 ES2.0 SoC. Make it so.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Tue, 19 Feb 2019 18:20:14 +0000 (19:20 +0100)]
mmc: tmio: Clear BUSWIDTH bit when WMODE bit is set
According to latest specification rev.0026, when HOST_MODE bit 0
(WMODE) is not set, HOST_MODE bit 8 (BUSWIDTH) is ignored. Clear
HOST_MODE bit 8 in such case and align the code with Linux and
avoid possible unforeseen issues.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Marek Vasut [Tue, 19 Feb 2019 00:07:21 +0000 (01:07 +0100)]
ARM: socfpga: Clear PL310 early in SPL
On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
will result in stale data in PL310 L2 cache controller. Even if the L2
cache controller is disabled via the CTRL register CTRL_EN bit, those
data can interfere with operation of devices using DMA, like e.g. the
DWMMC controller. This can in turn cause e.g. SPL to fail reading data
from SD/MMC.
The obvious solution here would be to fully reset the L2 cache controller
via the reset manager MPUMODRST L2 bit, however this causes bus hang even
if executed entirely from L1 I-cache to avoid generating any bus traffic
through the L2 cache controller.
This patch thus configures and enables the L2 cache controller very early
in the SPL boot process, clears the L2 cache and disables the L2 cache
controller again.
The reason for doing it in SPL is because we need to avoid accessing any
of the potentially stale data in the L2 cache, and we are certain any of
the stale data will be below the OCRAM address range. To further reduce
bus traffic during the L2 cache invalidation, we enable L1 I-cache and
run the invalidation code entirely out of the L1 I-cache.
Marek Vasut [Wed, 13 Feb 2019 20:50:25 +0000 (21:50 +0100)]
ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
AKASHI Takahiro [Mon, 25 Feb 2019 06:54:38 +0000 (15:54 +0900)]
cmd: add efidebug command
Currently, there is no easy way to add or modify UEFI variables.
In particular, bootmgr supports BootOrder/BootXXXX variables, it is
quite hard to define them as u-boot variables because they are represented
in a complicated and encoded format.
The new command, efidebug, helps address these issues and give us
more friendly interfaces:
* efidebug boot add: add BootXXXX variable
* efidebug boot rm: remove BootXXXX variable
* efidebug boot dump: display all BootXXXX variables
* efidebug boot next: set BootNext variable
* efidebug boot order: set/display a boot order (BootOrder)
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Since commit 914df75b0c97 ("efi_loader: fix EFI entry counting")
entry_count is already set to 1 before efi_bootmgr_load() is called. So we
should not increment it when entering the function.
Without the patch an assert error occurs in efi_get_variable() if DEBUG is
defined.
Jan Kiszka [Thu, 3 Jan 2019 08:08:42 +0000 (09:08 +0100)]
cmd: Kconfig: LED command depends on LED subsystems
Without CONFIG_LED, we get
cmd/built-in.o: In function `show_led_state':
cmd/led.c:40: undefined reference to `led_get_state'
cmd/built-in.o: In function `do_led':
cmd/led.c:99: undefined reference to `led_get_by_label'
cmd/led.c:108: undefined reference to `led_set_state'
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tom Rini [Wed, 20 Feb 2019 17:28:40 +0000 (12:28 -0500)]
Merge git://git.denx.de/u-boot-x86
- Add support for sound.
Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
board: toradex: turn off lcd backlight before OS handover
U-Boot typically tears down the display controller before handing
control over to Linux. On LCD displays disabling pixel clock leads to a
fading out effect with vertical/horizontal lines. Make sure to disable
back light before booting Linux.
Signed-off-by: Gerard Salvatella <gerard.salvatella@toradex.com> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Wed, 20 Feb 2019 12:17:29 +0000 (12:17 +0000)]
nyan-big: drop CONFIG_KEYBOARD
The CONFIG_KEYBOARD does nothing as it's legacy and unused
so just drop it from the config.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Wed, 20 Feb 2019 12:17:28 +0000 (12:17 +0000)]
Kconfig: tegra: Migrate TEGRA_KEYBOARD
Migrate TEGRA_KEYBOARD from headers to Kconfig, only the seaboard uses it but we
drop CONFIG_KEYBOARD as the driver doesn't use the legacy drv_keyboard_init.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Wed, 20 Feb 2019 12:17:27 +0000 (12:17 +0000)]
Kconfig: tegra: Migrate USB_EHCI_TEGRA
Migrate USB_EHCI_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peter.Chubb@data61.csiro.au Cc: Lucas Stach <dev@lynxeye.de> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Wed, 20 Feb 2019 12:17:26 +0000 (12:17 +0000)]
Kconfig: tegra: Migrate SYS_I2C_TEGRA
Migrate SYS_I2C_TEGRA from headers to Kconfig
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Heiko Schocher <hs@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peter.Chubb@data61.csiro.au Cc: Lucas Stach <dev@lynxeye.de> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jonathan Hunter [Tue, 12 Feb 2019 16:03:14 +0000 (16:03 +0000)]
ARM: tegra: Reserve 32MB for the Linux kernel
Booting recently Linux -next kernels on 32-bit Tegra devices has been
failing when using the 'multi_v7_defconfig' kenrel configuration because
the size of has grown such that it is overwriting the FDT blob.
Current Linux -next kernels built with the 'multi_v7_defconfig' have a
total size of ~19.5MB (where .text is ~12.5MB, .data is ~6.5MB and .bss
is ~0.5MB). Therefore, increase the memory location reserved for the
Linux kernel to 32MB from 16MB for 32-bit Tegra devices.
This change has been boot tested on Tegra20 Ventana, Tegra30 Cardhu and
Tegra124 Jetson TK1 with the Linux next tree (20190212).
Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Tristan Bastian [Thu, 14 Feb 2019 23:25:49 +0000 (00:25 +0100)]
ARM: tegra: enable ums on nyan boards
This patch enables UMS on the nyan devices like the nyan-big.
A patch like this has been sent in by Stephen Warren some time ago for
other tegra devices: commit e6607cffef965011ef0ddc0fbe6f4b7c0d53aeec.
But the nyan devices never received that functionality.
Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Tristan Bastian [Wed, 16 Jan 2019 18:49:55 +0000 (19:49 +0100)]
nyan-big: change spi delay
Internal keyboard of nyan-big is only working when cold booting by pressing [reload/refresh]+[power] button.
With this patch keyboard is working by only pressing [power] button.
Signed-off-by: Tristan Bastian <tristan-c.bastian@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Sun, 16 Sep 2018 17:22:58 +0000 (18:22 +0100)]
tegra20: common: fix USB_EHCI_TXFIFO_THRESH value
All other Tegra devices that define USB_EHCI_TXFIFO_THRESH use hex
representation, fix tegra20 to be the same format.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Peter Robinson [Sun, 16 Sep 2018 17:22:57 +0000 (18:22 +0100)]
tegra: cleanup dangling comments in include/configs
There's a number of dangling comments in various tegra configs post migrations
of various configs so lets clean them up.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Peter.Chubb@data61.csiro.au Cc: Lucas Stach <dev@lynxeye.de> Cc: Stefan Agner <stefan.agner@toradex.com> Cc: Alban Bedel <alban.bedel@avionic-design.de> Cc: Allen Martin <amartin@nvidia.com> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 17 Feb 2019 03:25:02 +0000 (20:25 -0700)]
x86: broadwell: Don't bother probing the PCH for pinctrl
At present the pinctrl probes the PCH but since it only uses it to obtain
a PCI address, this is no necessary. Avoiding this fixes one of the two
co-dependent loops in broadwell.
This driver really should be a proper pinctrl driver, but for now it
remains a syscon device.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:56 +0000 (20:24 -0700)]
sandbox: sound: Silence sound for testing
When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:55 +0000 (20:24 -0700)]
sound: Add support for Intel HDA
The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.
Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:54 +0000 (20:24 -0700)]
sound: Add uclass operations for beeping
Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:51 +0000 (20:24 -0700)]
pch: Add ioctl support
At present the PCH has 4 operations and these are reasonably widely used
in the drivers. But sometimes we want to add rarely used operations, and
each of these currently adds to the size of the PCH operations table.
Add an ioctl() method which can be easily expanded without any more impact
on the operations table.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:50 +0000 (20:24 -0700)]
sandbox: pch: Add a test for the PCH uclass
This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:49 +0000 (20:24 -0700)]
x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sun, 17 Feb 2019 03:24:48 +0000 (20:24 -0700)]
x86: link: Increase malloc size and decrease code size
At present link does not boot since it has outgrown its pre-relocation
malloc() size and its assigned code area. Increase the former and drop
EFI loader support, which adds about 45KB!
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log
