Sean Anderson [Sat, 4 Nov 2023 20:37:53 +0000 (16:37 -0400)]
test: spl: Add a test for NAND
Add a SPL test for the NAND load method. We use some different functions to
do the writing from the main test since things like nand_write_skip_bad
aren't available in SPL.
We disable BBT scanning, since scan_bbt is only populated when not in SPL.
We use nand_spl_loaders.c as it seems to be common to at least a few boards
already. However, we do not use nand_spl_simple.c because it would require
us to implement cmd_ctrl. The various nand load functions are adapted from
omap_gpmc. However, they have been modified for simplicity/correctness.
Sean Anderson [Sat, 4 Nov 2023 20:37:52 +0000 (16:37 -0400)]
nand: Add sandbox driver
Add a sandbox NAND flash driver to facilitate testing. This driver supports
any number of devices, each using a single chip-select. The OOB data is
stored in-band, with the separation enforced through the API.
For now, create two devices to test with. The first is a very small device
with basic ECC. The second is an 8G device (chosen to be larger than 32
bits). It uses ONFI, with the values copied from the datasheet. It also
doesn't need too strong ECC, which speeds things up.
Although the nand subsystem determines the parameters of a chip based on
the ID, the driver itself requires devicetree properties for each
parameter. We do not derive parameters from the ID because parsing the ID
is non-trivial. We do not just use the parameters that the nand subsystem
has calculated since that is something we should be testing. An exception
is made for the ECC layout, since that is difficult to encode in the device
tree and is not a property of the device itself.
Despite using file I/O to access the backing data, we do not support using
external files. In my experience, these are unnecessary for testing since
tests can generally be written to write their expected data beforehand.
Additionally, we would need to store the "programmed" information somewhere
(complicating the format and the programming process) or try to detect
whether block are erased at runtime (degrading probe speeds).
Information about whether each page has been programmed is stored in an
in-memory buffer. To simplify the implementation, we only support a single
program per erase. While this is accurate for many larger flashes, some
smaller flashes (512 byte) support multiple programs and/or subpage
programs. Support for this could be added later as I believe some
filesystems expect this.
To test ECC, we support error-injection. Surprisingly, only ECC bytes in
the OOB area are protected, even though all bytes are equally susceptible
to error. Because of this, we take care to only corrupt ECC bytes.
Similarly, because ECC covers "steps" and not the whole page, we must take
care to corrupt data in the same way.
Sean Anderson [Sat, 4 Nov 2023 20:37:51 +0000 (16:37 -0400)]
arch: sandbox: Add function to create temporary files
When working with sparse data buffers that may be larger than the address
space, it is convenient to work with files instead. Add a function to create
temporary files of a certain size.
Sean Anderson [Sat, 4 Nov 2023 20:37:49 +0000 (16:37 -0400)]
nand: Add function to unregister NAND devices
This performs the opposite of nand_register, allowing drivers to unregister
nand devices. This is probably unnecessary for most regular drivers, but we
expect sandbox drivers to get repeatedly bound/unbound, so this will help
avoid dangling pointers.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Sean Anderson [Sat, 4 Nov 2023 20:37:44 +0000 (16:37 -0400)]
spl: nand: Set bl_len to page size
Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned
access") there are no longer any users of nand_get_mtd. However, it is
still important to know what the page size is so we can allocate a
large-enough buffer. If the image size is not page-aligned, we will go off
the end of the buffer and clobber some memory.
Introduce a new function nand_page_size which returns the page size. For
most drivers it is easy to determine the page size. However, a few need to
be modified since they only keep the page size around temporarily.
It's possible that this patch could cause a regression on some platforms if
the offset is non-aligned and there is invalid address space immediately
before the load address. spl_load_legacy_img does not (except when
compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or
SPL_LOAD_IMX_CONTAINER (none in tree) would be affected.
All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q
which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the
i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a
little underflow.
Sean Anderson [Sat, 4 Nov 2023 20:37:43 +0000 (16:37 -0400)]
spl: legacy: Honor bl_len when decompressing
When allocating a buffer to load compressed data into, we need to ensure we
have enough space for over- and under-flow due to alignment. Otherwise we
will clobber the malloc bookkeeping data. Calculate the correct amount of
overhead and use it when determining the size.
Sean Anderson [Sat, 4 Nov 2023 20:37:42 +0000 (16:37 -0400)]
nand: spl_loaders: Only read enough pages to load the image
All other implementations of nand_spl_load_image only read as many pages as
are necessary to load the image. However, nand_spl_loaders.c loads the full
block. Align it with other load functions so that it is easier to
determine how large of a load buffer we need.
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Contrary to what the help message says, this is the number of pages per
block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and
SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to
SYS_NAND_BLOCK_PAGES.
Sean Anderson [Sat, 4 Nov 2023 20:37:40 +0000 (16:37 -0400)]
nand: Don't dereference NULL manufacturer_desc
When no manufacturer is matched, manufacturer_desc is NULL. Avoid
dereferencing it in that case.
Fixes: 4e67c571252 ("mtd,ubi,ubifs: sync with linux v3.15") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Svyatoslav Ryhel [Tue, 24 Oct 2023 07:49:03 +0000 (10:49 +0300)]
sysreset: tegra: create arch specific sysreset driver
Tegra uses built in Power Management Controller (PMC) to perform
CPU reset. Code to perform this was located in mach-tegra, so lest
create DM driver to handle this.
Svyatoslav Ryhel [Fri, 27 Oct 2023 08:26:09 +0000 (11:26 +0300)]
power: regulator: palmas: fix ldoln and ldousb detection
dev->driver_data will carry the tail of ldo if there is a number and
if there is no number it will be an error code, anyway it will not be
zero. This results in a wrong ldo regulator detection.
To avoid this check for non-numerical ldo first and then manipulate
dev->driver_data.
Svyatoslav Ryhel [Fri, 27 Oct 2023 08:26:08 +0000 (11:26 +0300)]
power: pmic: palmas: support TI TPS65913 PMIC
Existing PALMAS PMIC driver is fully compatible with TI TPS65913
PMIC found in many Tegra 4 devices, like Tegra Note 7 and ASUS
TF701T. TPS65913 shares same structure of regulators like TPS659038
so data can be reused.
Remove nvidia_board_late_init calls from board since this setup is
performed in board2 of mach-tegra. Call of nvidia_board_late_init
from within the board does not provide any additional data.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Transformer T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Board specific late init allows vendors to set up different device
or board specific env variables (like serial number, platform name).
In case this information is missing, u-boot will lack info regards
serial or platform.
To avoid this prior nvidia_board_late_init internal generic function
is called which fills required data. In this case platform name is
obtained from get_chip and serialno is filled with SoC id.
Though SoC id is not dedicated to be devices serial but it fits well
in case of restriction of data about device and since SoC is basically
a main chip of the device.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Transformers Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
ARM: tegra20: tegra30: support EBTUPDATE on non-encrypted devices
Re-crypt support was extended to devices without burnt SBK. In case
SBK is not set, place from where it is read is filled with zeroes.
This patch adds support for ebtupdate function to detect nosbk device
and avoid crypto operations for it.
Tested-by: Maksim Kurnosenko <asusx2@mail.ru> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
ARM: tegra114: enable base voltages setup from board
Tegra 4, same as Tegra 3, requires configuration of CPU and CORE
voltages in the SPL stage to boot properly. Expose function to be
able perform this configuration in the SPL section of the device
board.
mmc: tegra: get default-tap and default-trim from device tree
Default-tap and default-trim values are used for eMMC setup
mostly on T114+ devices. As for now, those values are hardcoded
for T210 and ignored for all other Tegra generations. Fix this
by passing tap and trim values from dts.
ARM: tegra210: set default-tap and default-trim values in sdhci nodes
Tegra MMC driver has hardcoded tap and trim values as for now.
Set default-tap and default-trim values in sdhci nodes to avoid
regressions in case Tegra MMC driver is upated to use dts values.
Tom Rini [Fri, 3 Nov 2023 13:53:01 +0000 (09:53 -0400)]
Merge tag 'qcom-pull-20231103' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
As discussed, here is the maintainers update for Snapdragon. Sumit Garg
who maintains a few of the Qualcomm platforms in U-boot has also been
added as a reviewer.
Simon Glass [Wed, 1 Nov 2023 17:17:50 +0000 (11:17 -0600)]
u_boot_pylib: Ensure subprocess is closed down
It isn't clear why we need to have two different paths for closing down
the pipe. Unify them and use the Python to avoid this warning:
subprocess.py:1127: ResourceWarning: subprocess 83531 is still running
Note that this code appears to originally have come from [1] and was
committed into the ChromeOS chromiumos/platform/crosutils repo in the
bin/cros_image_to_target.py file. The addition of the extra code path
came later, so that is chosen for the fixes tag.
Simon Glass [Mon, 30 Oct 2023 17:22:30 +0000 (10:22 -0700)]
buildman: Support upstream branch name containing /
Buildman assumes that branch names do not have a slash in them, since
slash is used to delimit remotes, etc. This means that a branch called
'WIP/tryme' in remote dm ends up being 'tryme'.
Adjust the logic a little, to try to accommodate this.
For now, no tests are added for this behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
binman: openssl: x509: ti_secure_rom: Add support for bootcore_opts
According to the TRMs of K3 platform of devices, the ROM boot image
format specifies a "Core Options Field" that provides the capability to
set the boot core in lockstep when set to 0 or to split mode when set
to 2. Add support for providing the same from the binman DTS. Also
modify existing test case for ensuring future coverage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 23 Oct 2023 07:52:43 +0000 (00:52 -0700)]
buildman: Include symbols in the read-only data section
When symbols switch between the inited data section and the read-only
data section their visbility changes, at present, with the -B option.
This is confusing, since adding 'const' to a variable declaration can
make it look like a significant improvement in bloat. But in fact
nothing has changed.
Add 'r' to the list of symbols types that are recorded, to correct this
problem. Add a constant to make it easier to find this code next time.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sat, 14 Oct 2023 20:40:27 +0000 (14:40 -0600)]
binman: Ensure attributes always come last in the metadata
cbfsutil changed to write zero bytes instead of 0xff when a small
padding must be added. Adjust the binman implementation to do the same.
Drop the code which looks for an unused attribute tag, since it is not
used. A future patch moves the attributes to the end of the header in
any case, so no data will follow the attributes.
Simon Glass [Sat, 14 Oct 2023 20:40:25 +0000 (14:40 -0600)]
binman: Reset missing bintools after testing
For tests which fake bintools being missing, we need to reset the list
afterwards, to ensure that future tests do not also see the bintools as
missing.
Reset the list when processing is complete.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Maxim Cournoyer [Fri, 13 Oct 2023 03:06:24 +0000 (23:06 -0400)]
patman: Add a 'keep_change_id' setting
A Change-Id can be useful for traceability purposes, and some projects
may wish to have them preserved. This change makes it configurable
via a new 'keep_change_id' setting.
Signed-off-by: Maxim Cournoyer <maxim.cournoyer@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 2 Nov 2023 14:12:33 +0000 (10:12 -0400)]
Merge tag 'i2cfixes-for-v2024-01-rc2' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2024.01-rc2
- nuvoton: support standard/fast/fast plus mode
- bootcount: remove legacy i2c driver and implement
DM based version
Bugfixes:
- designware_i2c: adjust timing calculation
SPL probing failed on the StarFive VisionFive 2 board
Heinrich fixed this, by syncing timing calculation with
linux implementation.
+ CI: Use OpenSBI 1.3.1 release for testing
+ riscv: Support resume after exception
+ rng: Support RNG provided by RISC-V Zkr ISA extension
+ board: starfive VF2: Support jtag
+ board: starfive VF2: Support TRNG driver
+ board: sifive unmatched: Move kernel load address
Paul Barker [Wed, 1 Nov 2023 20:05:53 +0000 (20:05 +0000)]
arm: mach-rmobile: Drop <common.h>
For most source files we can just drop <common.h>. We need to add an
include for <asm/u-boot.h> in a couple of places. Also sort the include
list in memmap-gen3.c while we're here.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Chanho Park [Wed, 1 Nov 2023 12:16:50 +0000 (21:16 +0900)]
rng: Add StarFive JH7110 RNG driver
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Samuel Holland [Tue, 31 Oct 2023 05:37:20 +0000 (00:37 -0500)]
riscv: Weakly define invalidate_icache_range()
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().
Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Samuel Holland [Tue, 31 Oct 2023 05:35:41 +0000 (00:35 -0500)]
riscv: Align the trap handler to 64 bytes
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."
Reported-by: Madushan Nishantha <jlmadushan@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yong-Xuan Wang [Thu, 26 Oct 2023 03:22:52 +0000 (03:22 +0000)]
board: sifive: unmatched: move kernel load address to 0x80200000
U-boot initially loads the kernel image to the kernel_addr_r, and
subsequently relocates it to memory address 0x80200000. Setting
kernel_addr_r to 0x80200000 can eliminate one copy operation.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Yang Xiwen [Thu, 17 Aug 2023 17:04:02 +0000 (01:04 +0800)]
clk: also handle ENOENT in *_optional functions
If the device does not specify any clocks in device tree, these
functions will return PTR_ERR(-ENOENT). This is not the intended
behavior and does not comply with linux kernel CCF. Fix that by
returning NULL under such circumstances instead.
Maksim Kiselev [Tue, 5 Sep 2023 22:16:49 +0000 (01:16 +0300)]
clk: use private clk struct in CLK_CCF's enable/disable functions
In clk_enable()/clk_disable() functions, when CCF is activated,
we must pass a private clk struct to enable()/disable() ops functions.
Otherwise, the use of a container_of() construction within these ops
should be banned. Because passing a non-private clk struct to
container_of() results in an out of range error.
At the moment, clk-mux, clk-fixed-factor, clk-gate and possibly other
clocks use container_of() in their enable()/disable() functions.
Therefore, for these functions to work correclty, private clk struct
must be passed.
Eugen Hristev [Mon, 19 Jun 2023 10:47:52 +0000 (13:47 +0300)]
clk: fix count parameter type for clk_release_all
The second parameter for clk_release_all is used as an unsigned
(which makes sense) but the function prototype declares it as an int.
This causes warnings/error like such below:
include/clk.h:422:48: error: conversion to ‘int’ from ‘unsigned int’ may change the sign of the result [-Werror=sign-conversion]
422 | return clk_release_all(bulk->clks, bulk->count);
To fix this, changed the type of the count to `unsigned int`
drivers: clk: Adjust temp var data type to properly match that of struct clk_ops
In commit 5c5992cb90cf ("clk: Add debugging for return values"), a
temporary storage variable was added around the ops->get_rate() call
inside clk_get_rate(), so that the result could be passed through
log_ret.
This temporary variable was declared as an int, yet when we look in
struct clk_ops, we can see this needs to be a ulong:
ulong (*get_rate)(struct clk *clk);
This was resulting in a signed to unsigned casting error on our
builds, where a clock value of 0xABCDABCD was being incorrectly cast
to 0xFFFFFFFFABCDABCD.
Simon Glass [Tue, 24 Oct 2023 18:17:36 +0000 (07:17 +1300)]
bootstd: Handle a few special cases in cmdline_set_arg()
Two bugs have appeared:
- arguments can have an equals sign embedded in them, which must be
considered part of the value
- arguments must fully match the name; partial matches should be
ignored
Compiling sandbox_defconfig with CONFIG_BOOTSTD=n fails:
/usr/bin/ld: drivers/mtd/spi/sf_bootdev.o:
in function `sf_get_bootflow':
/drivers/mtd/spi/sf_bootdev.c:43:(.text+0x96):
undefined reference to `bootmeth_set_bootflow'
Add the missing Kconfig dependency.
Fixes: Fixes: 0c1f4a9fb13a ("bootstd: Add a SPI flash bootdev") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log
