The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.
A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.
This commit adds the missing identification of the SelectMAP mode.
Versal NET clock node should use "xlnx,versal-net-clk", "xlnx,versal-clk"
compatible string that's why it is not necessary to define Versal NET
specific compatible string if there is no any other change needed. It can
be get back if there is a need to differentiate clock support between
Versal and Versal NET.
Michal Simek [Wed, 27 Sep 2023 09:57:48 +0000 (11:57 +0200)]
arm64: zynqmp: Do not use '_' in DT node names
Using '_' is not recommended for node names. Use '-' instead.
Pretty much run seds below for node names.
s/heartbeat_led/heartbeat-led/
s/gtr_sel/gtr-sel/
s/zynqmp_ipi/zynqmp-ipi/
s/nvmem_firmware/nvmem-firmware/
s/soc_revision/soc-revision/
Xilinx was using in past is-dual property for QSPIs to reflect their
configurations. But handling for them never reached upstream code that's
why better to remove them.
Michal Simek [Wed, 27 Sep 2023 09:53:36 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for zcu670-revA
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Michal Simek [Wed, 27 Sep 2023 09:53:35 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for VPXA2785
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Michal Simek [Wed, 27 Sep 2023 09:53:34 +0000 (11:53 +0200)]
arm64: zynqmp: Describe i2c structures for SCs
Generic system controller (SC) covers connection defined by specification
but different boards have different i2c devices. That's why describe i2c
devices available on multiple boards.
Michal Simek [Wed, 27 Sep 2023 09:53:33 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for SC revC
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Michal Simek [Wed, 27 Sep 2023 09:53:32 +0000 (11:53 +0200)]
arm64: zynqmp: Create description for generic SC (vpk120-revB)
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Michal Simek [Wed, 27 Sep 2023 09:53:31 +0000 (11:53 +0200)]
arm64: zynqmp: Add support for vpk120-revA
Board contains two systems. The primary is Versal VP1202 ACAP device and
the secondary is ZynqMP zu4 which acts as system controller. The patch is
describing only ZynqMP system controller part.
Michal Simek [Fri, 22 Sep 2023 10:35:42 +0000 (12:35 +0200)]
ARM: zynq: Describe nand device in DT
Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.
Error shown by Linux kernel:
pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22
Michal Simek [Fri, 22 Sep 2023 10:35:41 +0000 (12:35 +0200)]
arm64: zynqmp: Sync licenses with Linux kernel
There is difference between licenses in the Linux kernel and there
shouldn't be any diff because all changes are coming from the same source
at the same time. The difference is really in a time when they were
upstreamed. That's why sync it up.
Michal Simek [Fri, 22 Sep 2023 10:35:37 +0000 (12:35 +0200)]
arm64: xilinx: Remove address/size-cells from gem nodes
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Michal Simek [Fri, 22 Sep 2023 10:35:36 +0000 (12:35 +0200)]
arm64: xilinx: Put ethernet phys to mdio node
All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.
Michal Simek [Fri, 22 Sep 2023 10:35:33 +0000 (12:35 +0200)]
arm64: xilinx: Use lower case for partition address
Lower case should be used for register address.
Issue is reported as:
flash@0: partitions: Unevaluated properties are not allowed
('partition@22A0000' was unexpected)
Michal Simek [Mon, 18 Sep 2023 14:09:18 +0000 (16:09 +0200)]
arm64: zynqmp: Rename dt overlay file names from dts to dtso
Use dtso suffix instead of dts. Build option was introduced by
commit a0f9a77912b2 ("kbuild: Allow DTB overlays to built from .dtso named
source files").
For Xilinx ZynqMP SOC new parameter was added and now it can
set 7 parameters for its pins. Pinmux status command will
print the status of these parameters for each pin. But
current print buffer length is only 80 characters long, increase it
to 90 to print all the parameters without truncation.
net: zynq_gem: Update the MDC clock divisor in the probe function
MDC clock change needs to be done when the driver probe function
is called as mdio is enabled at probe and not when the ethernet starts.
Setup the MDC clock at the probe itself.
To quote the author:
This series tidies up SPL a little and adds some core ofnode functions
needed to support Universal Payload. It also includes a few minor
fix-ups for sandbox.
For SPL the changes include CONFIG naming, removing various #ifdefs and
tidying up the FIT code.
One notable piece of the ofnode improvements is support for flattening a
livetree. This should be useful in future as we move FDT fixups to use
the ofnode API.
Simon Glass [Tue, 26 Sep 2023 14:14:58 +0000 (08:14 -0600)]
pci: serial: Support reading PCI-register size with base
The PCI helpers read only the base address for a PCI region. In some cases
the size is needed as well, e.g. to pass along to a driver which needs to
know the size of its register area.
Update the functions to allow the size to be returned. For serial, record
the information and provided it with the serial_info() call.
A limitation still exists in that the size is not available when OF_LIVE
is enabled, so take account of that in the tests.
Simon Glass [Tue, 26 Sep 2023 14:14:57 +0000 (08:14 -0600)]
dm: core: Tweak device_is_on_pci_bus() for code size
This function cannot return true if PCI is not enabled, since no PCI
devices will have been bound. Add a check for this to reduce code size
where it is used.
Simon Glass [Tue, 26 Sep 2023 14:14:55 +0000 (08:14 -0600)]
spl: Add C-based runtime detection of SPL
The spl_phase() function indicates whether U-Boot is in SPL and before
or after relocation. But sometimes it is useful to check for SPL with
zero code-size impact. Since spl_phase() checks the global_data flags,
it does add a few bytes.
Add a new spl_in_proper() function to check if U-Boot proper is
running, regardless of the relocation status.
Simon Glass [Tue, 26 Sep 2023 14:14:51 +0000 (08:14 -0600)]
bloblist: Support initing from multiple places
Typically the bloblist is set up after the devicetree is present. This
makes sense because bloblist may use malloc() to allocate the space it
needs.
However sometimes the devicetree itself may be present in the bloblist.
In that case it is at a known location in memory so we can init the
bloblist very early, before devicetree.
Add a flag to indicate whether the bloblist has been inited. Add a
function to init it only if needed. Use that in the init sequence.
Simon Glass [Tue, 26 Sep 2023 14:14:48 +0000 (08:14 -0600)]
sandbox: Init the EC properly even if no state file is available
This currently relies on sandbox attempting to read a state file. At
present it always does, even when there is no state file, in which case it
fails, but still inits the EC.
That is a bug, so update this driver to set the current image always, even
if no state is read.
Simon Glass [Tue, 26 Sep 2023 14:14:43 +0000 (08:14 -0600)]
dm: core: Add a way to convert a devicetree to a dtb
Add a way to flatten a devicetree into binary form. For livetree this
involves generating the devicetree using fdt_property() and other calls.
For flattree it simply involves providing the buffer containing the tree.
Simon Glass [Tue, 26 Sep 2023 14:14:41 +0000 (08:14 -0600)]
dm: core: Add a way to copy a node
Add a function to copy a node to another place under a new name. This is
useful at least for testing, since copying a test node with existing
properties is easier than writing the code to generate it all afresh.
Simon Glass [Tue, 26 Sep 2023 14:14:39 +0000 (08:14 -0600)]
dm: core: Tidy up comments in the ofnode tests
Add comments to the functions where the test name does not indicate what
is being tested. Rename functions in a few cases, so that a search for the
function will also file its test.
Simon Glass [Tue, 26 Sep 2023 14:14:35 +0000 (08:14 -0600)]
spl: Use the correct FIT_..._PROP constants
Rather than open-coding the property names, use the existing constants
provided for this purpose. This better aligns the simple-FIT code with
the full FIT implementation.
Simon Glass [Tue, 26 Sep 2023 14:14:32 +0000 (08:14 -0600)]
spl: Remove #ifdefs with BOOTSTAGE
This feature has some helpers in its header file so that its functions
resolve to nothing when the feature is disabled. Add a few more and use
these to simplify the code.
With this there are no more #ifdefs in board_init_r()
Simon Glass [Tue, 26 Sep 2023 14:14:24 +0000 (08:14 -0600)]
spl: Create proper symbols for enabling the malloc() pool
For U-Boot proper we have CONFIG_SYS_MALLOC_F which indicates that a
malloc() pool is available before relocation.
For SPL we only have CONFIG_SPL_SYS_MALLOC_F_LEN which indicates the
size of the pool.
In various places we use CONFIG_SPL_SYS_MALLOC_F_LEN == 0 to indicate
that there is no pool.
This differing approach is confusing. Add a new CONFIG_SPL_SYS_MALLOC_F
symbol for SPL (and similarly for TPL and VPL). Tidy up the Kconfig
help for clarity.
For now these symbols are not used. That is cleaned up in the following
patches.
Simon Glass [Tue, 26 Sep 2023 14:14:19 +0000 (08:14 -0600)]
spl: mx6: powerpc: Drop the condition on timer_init()
It doesn't make sense to have some boards do this differently. Drop the
condition in the hope that the maintainers can figure out any run-time
problems.
This has been tested on qemu-ppce500
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Simon Glass [Tue, 26 Sep 2023 14:14:17 +0000 (08:14 -0600)]
spl: Rename SYS_SPL_ARGS_ADDR to SPL_PAYLOAD_ARGS_ADDR
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.
Simon Glass [Tue, 26 Sep 2023 14:14:16 +0000 (08:14 -0600)]
spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support
* Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove
timer0, we have its clocks set up in clk-data now
* Remove hbmc node as support is buggy and needs to be fixed
* Remove aliases and chosen node, use them from Kernel
* Remove /delete-property/ and clock-frequency from sdhci,
usbss, and mcu_uart nodes as we have them in clk and dev data
* Remove dummy_clocks as they are not needed
* Remove cpsw node as it is not required since it has been fixed
in U-Boot
* Remove pcie nodes, they are not needed
* Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk
for which support is not yet added
* Change secproxy nodes to their Linux definitions
* Remove overriding of ti,cluster-mode in MAIN R5 to default to
lockstep mode same as Kernel
* Retain tps6594 node as TPS6594 PMIC support is still under
review in the Kernel [1], cleanup will be taken post its merge
Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code
although it could've been automatically done by U-Boot is to resolve
some of the dependencies that R5 file requires.
Also remove duplicate phandles while making this shift as well as remove
firmware-loader as it serves no purpose without "phandlepart" property.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Kernel commit d93036b47f35 ("arm64: dts: ti: k3-j721e-mcu_wakeup: Add
HyperBus node") was merged to kernel without its dependent patch [1].
Similar fix is needed in U-Boot, and hbmc currently breaks boot. Till
this gets fixed in U-Boot, disable the config by default so that the
hbmc probe that happens in board/ti/j721e/evm.c will not take place
and lead to boot failure.
drivers: firmware: ti_sci: Get SCI revision only if TIFS/SYSFW is up
When setting up boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which calls dm_timer_init()
which then gets the tick-timer: mcu_timer0. mcu_timer0 uses k3_clks
(clock controller) and k3_pds (power controller) from the dmsc node that
forces probe of the ti_sci driver of TIFS that hasn't been loaded yet!
Running ti_sci_cmd_get_revision from the probe leads to panic since no
TIFS and board config binaries have been loaded yet. Resolve this by
moving ti_sci_cmd_get_revision to ti_sci_get_handle_from_sysfw as a
common point of invocation for both legacy and combined boot flows.
Before doing this, it is important to go through whether any sync points
exist where revision is needed before ti_sci_get_handle_from_sysfw is
invoked. Going through the code along with boot tests on both flows
ensures that there are none.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
arm: mach-k3: j721e_init: Move clk_k3 probe before loading TIFS
When setting boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which eventually calls
dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
need to set up the clocks before using the timer, move clk_k3 driver
probe before k3_sysfw_loader to ensure we have all necessary clocks set
up before.
Roger Quadros [Fri, 29 Sep 2023 13:46:46 +0000 (16:46 +0300)]
arm: dts: k3-am625-sk: Mark dependent nodes for pre-relocation phase
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
main_conf is required for phy_gmii_sel.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes the below dts warnings:
<stdout>: Warning (reg_format): /bus@f0000/syscon@100000/phy@4044:reg: property has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (reg_format): /bus@f0000/ethernet@8000000/ethernet-ports/port@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (unit_address_vs_reg): /bus@f0000/syscon@100000: node has a unit name, but no reg or ranges property
<stdout>: Warning (pci_device_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
<stdout>: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/syscon@100000/phy@4044: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/syscon@100000/phy@4044: Relying on default #size-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/ethernet@8000000/ethernet-ports/port@1: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f0000/ethernet@8000000/ethernet-ports/port@1: Relying on default #size-cells value
<stdout>: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Nishanth Menon <nm@ti.com>
projects / u-boot.git / log
