Ofer Heifetz [Wed, 29 Aug 2018 08:56:06 +0000 (11:56 +0300)]
mtd: pxa3xx_nand: Increase the initial chunk size
The chunk size represents the size of the data chunks, which
is used by the controllers that allow to split transferred data.
However, the initial chunk size is used in a non-split way,
during device identification. Therefore, it must be large enough
for all the NAND commands issued during device identification.
This includes NAND_CMD_PARAM which was recently changed to
transfer up to 2048 bytes (for the redundant parameter pages).
Thus, the initial chunk size should be 2048 as well.
On Armada 370/XP platforms (NFCv2) booted without the keep-config
devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM
command:
[..]
pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device
pxa3xx-nand f10d0000.nand: Wait time out!!!
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38
nand: Micron MT29F8G08ABABAWP
nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224
This commit is taken from Linux:
'commit c7f00c29aa8'
("mtd: pxa3xx_nand: Increase the initial chunk size")
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Ofer Heifetz [Wed, 29 Aug 2018 08:56:05 +0000 (11:56 +0300)]
nand: pxa3xx: Increase READ_ID buffer and make the size static
The read ID count should be made as large as the maximum READ_ID size,
so there's no need to have dynamic size. This commit sets the hardware
maximum read ID count, which should be more than enough on all cases.
Also, we get rid of the read_id_bytes, and use a macro instead.
This commit is taken from Linux:
'commit b226eca2088'
("nand: pxa3xx: Increase READ_ID buffer and make the size static")
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Ofer Heifetz [Wed, 29 Aug 2018 08:56:04 +0000 (11:56 +0300)]
mtd: nand: pxa3xx-nand: fix random command timeouts
When 2 commands are submitted in a row, and the second is very quick,
the completion of the second command might never come. This happens
especially if the second command is quick, such as a status read
after an erase
This patch is taken from Linux:
'commit 21fc0ef9652f'
("mtd: nand: pxa3xx-nand: fix random command timeouts")
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Ofer Heifetz [Wed, 29 Aug 2018 08:56:03 +0000 (11:56 +0300)]
mtd: nand: pxa3xx_nand: fix early spurious interrupt
When the nand is first probe, and upon the first command start, the
status bits should be cleared before the interrupts are unmasked.
This commit is taken from Linux:
'commit 0b14392db2e'
("mtd: nand: pxa3xx_nand: fix early spurious interrupt")
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Since the pxa3xx_nand driver was added there has been a discrepancy in
pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min.
This brings us into line with the current Linux code.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Ofer Heifetz [Wed, 29 Aug 2018 08:56:01 +0000 (11:56 +0300)]
mtd: nand: pxa3xx_nand: use nand_to_mtd()
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the
one that is already part of struct nand_chip. This brings us in line
with current U-boot and Linux conventions.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
The initial buffer is used for the initial commands used to detect
a flash device (STATUS, READID and PARAM).
ONFI param page is 256 bytes, and there are three redundant copies
to be read. JEDEC param page is 512 bytes, and there are also three
redundant copies to be read. Hence this buffer should be at least
512 x 3. This commits rounds the buffer size to 2048.
This commit is taken from Linux:
'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size")
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
Marek Behún [Fri, 17 Aug 2018 10:58:51 +0000 (12:58 +0200)]
phy: marvell: Support changing SERDES map in board file
This adds a weak definition of comphy_update_map to comphy_core,
which does nothing. If this function is defined elsewhere, for example
in board file, the board file can change some parameters of SERDES
configuration.
This is needed on Turris Mox, where the SERDES speed on lane 1 has to
be set differently when SFP module is connected and when Topaz Switch
module is connected.
This is a temporary solution. When the comphy driver for armada-3720
will be added to the kernel, the comphy driver in u-boot shall also be
updated and this should be done differently then.
Signed-off-by: Marek Behun <marek.behun@nic.cz> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham [Fri, 17 Aug 2018 08:47:42 +0000 (20:47 +1200)]
ARM: mach-mvebu: handle fall-back to UART boot
The bootROM in the Armada-38x (and similar) SoC has two modes for UART
boot. The first is when the normal boot media is blank (or otherwise
missing the kwb header). The second is when the boot sequence has been
interrupted with the magic byte sequence on the UART lines.
In the first mode the bootROM routine and error code register will
indicate that there was an error booting from the configured media in
bits 7:0. In the second mode there is no error to indicate but the boot
source is provided via bits 31:28.
Handle both situations so that kwboot can be used for both boot
strapping a blank board and for intercepting a regular boot sequence.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Stefan Roese <sr@denx.de>
Jon Nettleton [Mon, 13 Aug 2018 15:24:38 +0000 (18:24 +0300)]
tools: kwboot: Make kwboot more robust on a38x
This patch accomplishes 2 things to make the kwboot procedure
on the a38x more reliable.
1) We fill the tty with 1K of the magic bootparam. This helps
with the timing of where the microcode picks up in the read of
the line to ensure we actually catch the break to go into recovery
mode
2) Before starting the xmodem transfer we sleep for 2 seconds
and then flush the line. This allows all the magic bootparam
to be flushed from the line and makes the xmodem transfer reliable
and removes the Bad message failures.
Signed-off-by: Jon Nettleton <jon@solid-run.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
These comments were copied from the Linux kernel driver in
drivers/platform/x86/intel_scu_ipc.c
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have I2C#6 working, it's time to add a corresponsing
ACPI binding.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have the pinctrl driver for Merrifield in place we can make
use of it and set I2C#6 pins appropriately.
Initial configuration came from the firmware. Which quite likely has
been used in the phones, where that is not part of Atom peripheral, is
in use. Thus we need to override the leftover.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: tangier: pinmux: add API to configure protected pins
This API is going to be used to configure some pins that are protected
for simple modification.
It's not a comprehensive pinctrl driver but can be turned into one
when we need this in the future. Now it is planned to be used only
in one place. So that's why I decided not to pollute the codebase with a
full-blown pinctrl-merrifield nobody will use.
This driver reads corresponding fields in DT and configures pins
accordingly.
The "protected" flag is used to distinguish configuration of SCU-owned
pins from the ordinary ones.
The code has been adapted from Linux work done by Andy Shevchenko
in pinctrl-merrfifield.c
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix build warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This interface will be used to configure properly some pins on
Merrifield that are shared with SCU.
scu_ipc_raw_command() writes SPTR and DPTR registers before sending
a command to SCU.
This code has been ported from Linux work done by Andy Shevchenko.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
m68k: fix multiple memory accesses on swap operations
On a
u32 val = __sw32(*addr);
multiple memory accesses are not welcome, since "addr" may
be an IO peripheral register address.
This patch changes __sw16/32 to perform a single memory
access for the source value.
Marek Vasut [Fri, 24 Aug 2018 19:43:17 +0000 (21:43 +0200)]
sh: tmu: Clean up register usage
The code uses all in all three TMU registers, drop the massive
register layout structures and just define the required timer
registers and use them throughout the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Fri, 24 Aug 2018 19:34:07 +0000 (21:34 +0200)]
sh: tmu: Clean up CONFIG_SH_TMU_CLK_FREQ
The R-Car Gen2 feeds the TMU with CONFIG_SYS_CLK_FREQ / 2,
while the old SH parts use CONFIG_SYS_CLK_FREQ directly.
Just put this into the TMU implementation and drop the
CONFIG_SH_TMU_CLK_FREQ config option.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Fri, 24 Aug 2018 19:23:04 +0000 (21:23 +0200)]
sh: tmu: Inline tmu_timer_{start,stop}()
These functions are always called for timer = 0, so drop the
timer check. Since these functions are called from one place
only and they are reduced to one line of code, just inline
them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Stratix10 combines the u-boot-spl image into the fpga configuration
bitstream so that the SDM can load the processors memory. This
process requires a hex format of the u-boot-spl image.
CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex"
Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.
If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Adam Ford [Mon, 3 Sep 2018 08:47:52 +0000 (03:47 -0500)]
MMC: davinici_mmc: Enable CD and WP with DM and OF_CONTROL
When used with a device tree, this will extract the card detect
and write protect pins from the device tree and configure them
accordingly. This assumes the GPIO_ACTIVE_LOW/HIGH is supported
by da8xx_gpio.
Adam Ford [Sun, 19 Aug 2018 16:11:03 +0000 (11:11 -0500)]
ARM: am3517_evm: Disable DM_I2C_COMPAT
DM_I2C_COMPAT is somehow being enabled outside of Kconfig, so
this explicitly undefines it in the header file, and brackets
the I2C initialization around an #ifdef to not manually
initialize the I2C controller when the DM_I2C is enabled.
Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Derald D. Woods <woods.technical@gmail.com>
Adam Ford [Mon, 3 Sep 2018 19:05:41 +0000 (14:05 -0500)]
ARM: omap3_logic: Enable DM_PMIC and DM_REGULATOR
Enabling DM_PMIC, DM_REGULATOR_FIXED, and DM_REGULATOR_GPIO
gives us the ability to better monitor voltages and enable
hardware through the device tree. The TL4030 (TPS65950) is
not yet migrated to DM, so this patch only enables the fixed
and GPIO controlled regulators.
With DM enabled, this patch enables DM_SERIAL and removes
the NS16550 initialization from da850_lowlevel since the driver
will take care of that itself.
Adam Ford [Thu, 9 Aug 2018 11:15:12 +0000 (06:15 -0500)]
MMC: Enable DM_MMC for Davinci
With CONFIG_BLK becoming a requirement, the Davinci MMC driver
needs to be updated with DM_MMC support. Since SPL is tiny and
many boards do not support DM in SPL, this retains the backwards
compatibility for those boards who need to initialize MMC manually
in SPL.
Signed-off-by: Peter Howard <phoward@gme.net.au> Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 3 Sep 2018 18:56:47 +0000 (13:56 -0500)]
ARM: omap3_logic: Enable Pinctrl
The simple pinctrl driver currently available works with the omap3.
Enabling this will use the device tree to automatically set the
pin-muxing for various drivers.
Adam Ford [Tue, 21 Aug 2018 12:16:56 +0000 (07:16 -0500)]
mmc: omap_hsmmc: Make DM_GPIO calls dependent on DM_GPIO
The getcd and getwp functions when DM_MMC is enabled are
assumming the DM_GPIO is enabled. In cases (like SPL) where
DM_GPIO may not be enabled, wrap these calls in an #ifdef
Adam Ford [Tue, 21 Aug 2018 01:43:00 +0000 (20:43 -0500)]
DM: serial: ti_omap3_common: Don't define serial unless !DM_SERIAL
The serial port was being manually configured during SPL build,
however in preparation to allow DM in SPL, this needs to change
to be based on whether or not DM_SERIAL is enabled because, soon
the assumption that SPL means no DM may not be accurate.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Tue, 21 Aug 2018 01:34:00 +0000 (20:34 -0500)]
ARM: mach-omap2: Don't initialize I2C if DM_I2C is enabled
boot-common.c checks to see if I2C is enabled in SPL, but
it doens't check for DM_I2C before initializing it. This
will now only initialize the I2C is the DM_I2C is not enabled
to avoid initializing it more than once.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Tue, 21 Aug 2018 01:27:48 +0000 (20:27 -0500)]
DM: omap_gpio: Reduce overhead when used with OF_PLATDATA
Platforms with limited resources in SPL may enable OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Tue, 21 Aug 2018 01:24:35 +0000 (20:24 -0500)]
DM: OMAP24XX_I2C: Reduce overhead when used with OF_PLATDATA
Platforms with limited resources in SPL may enably OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Adam Ford [Tue, 21 Aug 2018 01:24:34 +0000 (20:24 -0500)]
DM: I2C: Reduce overhead when used with OF_PLATDATA
Platforms with limited resources in SPL may enably OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.
Adam Ford [Fri, 17 Aug 2018 04:13:34 +0000 (23:13 -0500)]
DM: GPIO: Fix da8xx GPIO indexing over GPIO 32
The GPIO banks are broken up into two 16-bit registers for each
bank set. Unfortunately, the math that determines how to shift
blindly shifted by the number of the gpio. This worked for gpio
numbers under 32, but higher gpio's are broken. This fixes the
gpio index, so the bank is passed and the shift amount within
the register is passed now instead of the gpio number.
Fixes: 8e51c0f25406("dm: gpio: Add DM compatibility to
GPIO driver for Davinci")
Adam Ford [Wed, 15 Aug 2018 18:22:03 +0000 (13:22 -0500)]
ARM: configs: Add da850evm_nand to boot from NAND
The DA850-EVM supports booting from NAND when used with the
UI expander board. da850evm_nand will create an ais file
that can be burned to NAND and booted while storing the env in
NAND along with some partitions tables for storing kernel,
dtb and rootfs in NAND.
include: am654_evm: Establish initial environment for SD card boot
Create a basic U-Boot environment that allows the automatic loading
of a Linux Kernel located at /boot/Image and an associated device tree
blob located at /boot/k3-am654-base-board.dtb from the secondary
partition of an ext4-formatted SD card on the AM654x EVM. Furthermore
the boot.scr and uEnv.txt detection and loading schemes are supported
in a manner already known from other TI platforms.
Note that this is intended to be a starting point to enable initial
board use and will most certainly get extended and refactored as
different boot media become available.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Mon, 27 Aug 2018 10:27:51 +0000 (15:57 +0530)]
remoteproc: Introduce K3 system controller
K3 specific SoCs have a dedicated microcontroller for doing
resource management. Any HLOS/firmware on compute clusters should
load a firmware to this microcontroller before accessing any resource.
Adding support for loading this firmware.
After the K3 system controller got loaded with firmware and started
up it sends out a boot notification message through the secure proxy
facility using the TI SCI protocol. Intercept and receive this message
through the rproc start operation which will need to get invoked
explicitly after the firmware got loaded.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Lokesh Vutla [Mon, 27 Aug 2018 10:27:50 +0000 (15:57 +0530)]
remoteproc: Allow for individual remoteproc initialization
Existing rproc_init() api tries to initialize all available
remoteproc devices. This will fail when there is dependency
among available remoteprocs. So introduce a separate api
that allows to initialize remoteprocs individually based
on id.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Lokesh Vutla [Mon, 27 Aug 2018 10:27:47 +0000 (15:57 +0530)]
mailbox: Allow attaching private data for mbox_chan
Sometimes mbox controllers wants to store private data in
mbox_chan so that it can be used at a later point of time.
Adding support for hooking private data.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
sysreset: Add TI System Control Interface (TI SCI) sysreset driver
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.
This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
projects / u-boot.git / log
