The R5 SPL on J7200 SoCs will be limited to booting just the
MCU R5FSS0 R5F core in LockStep-mode at present, so add the
two required environment variables 'addr_mcur5f0_0load' and
'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot
logic. The firmware name used is also different from that on
J721E SoCs.
Suman Anna [Mon, 17 Aug 2020 23:15:14 +0000 (18:15 -0500)]
configs: j7200_evm_a72: Enhance bootcmd to start remoteprocs
The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.
The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.
Suman Anna [Mon, 17 Aug 2020 23:15:12 +0000 (18:15 -0500)]
env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200
The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit 0b4ab9c9a754 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").
Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.
The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw
The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.
Suman Anna [Mon, 17 Aug 2020 23:15:11 +0000 (18:15 -0500)]
arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Suman Anna [Mon, 17 Aug 2020 23:15:09 +0000 (18:15 -0500)]
armv8: K3: j7200: Add custom MMU support
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.
The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.
Suman Anna [Mon, 17 Aug 2020 23:15:08 +0000 (18:15 -0500)]
remoteproc: k3-r5: Add support for J7200 R5Fs
The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.
The revised IP has the following two new features:
1. TCMs are auto-initialized during module power-up, and the behavior
is programmable through a MMR bit controlled by System Firmware.
2. The LockStep-mode allows the Core1 TCMs to be combined with the
Core0 TCMs effectively doubling the amount of TCMs available.
The LockStep-mode on previous SoCs could only use the Core0 TCMs.
This combined TCMs appear contiguous at the respective Core0 TCM
addresses.
Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.
Suman Anna [Mon, 17 Aug 2020 23:15:07 +0000 (18:15 -0500)]
dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs
The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.
These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.
Suman Anna [Mon, 17 Aug 2020 21:57:36 +0000 (16:57 -0500)]
env: ti: j721e-evm: Limit scope of rproc env variables used by R5 SPL
The commit 316c927135d6 ("include: configs: j721e_evm: Add env variables
for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env
variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load'
and 'name_mcur5f0_0fw' to the generic environment, but these are only
needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main
R5FSS0 Core0 on J721E SoCs.
These are not really needed for A72 U-Boot, so limit the scope of
these variables only to R5 SPL. While at this, also fix the loadaddr
variable values to include the hex prefix like with other such env
variables.
Cc: Keerthy <j-keerthy@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 21:57:35 +0000 (16:57 -0500)]
configs: j721e_evm: Add Main R5FSS1 Core1 to default rproc boot list
The default rproc list currently used by A72 U-Boot to boot various
remote processors include the Main R5FSS0 (Split-mode) Core1, Main
R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster
is configured for Split mode by default in the dts now, so add the
Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This
core is now booted after the Main R5FSS1 Core0 and before the DSPs.
The order of the rprocs to boot can always be changed at runtime if
desired by overwriting the 'rproc_fw_binaries' environment variable
at U-boot prompt. Note that the R5FSS Core1 cannot be booted before
its associated Core0.
Suman Anna [Mon, 17 Aug 2020 21:57:34 +0000 (16:57 -0500)]
arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-mode
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.
board: ti: j721e: Add support for HyperFlash detection
On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.
Tom Rini [Mon, 7 Sep 2020 12:49:50 +0000 (08:49 -0400)]
Merge tag 'efi-2020-10-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc4
Bug fixes are provided in the following areas:
* convert file system debug and print messages go log messages
* convert UEFI booting messages to log messages
* UEFI related code clean up and simplification
* Eliminate superfluous enum value EFI_TABLE_END.
* Use correct variable type for the memory type.
* Check validity of memory type.
* Make efi_build_mem_table static.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
defconfig: espressobin: Add support for ISSI SPI flashes
Enable support of ISSI SPI flashes found on EspressoBIN boards
Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/61455 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de>
zachary [Fri, 28 Aug 2020 14:56:29 +0000 (16:56 +0200)]
phy: marvell: a3700: add sata comphy on lane 2 with invert option
- This patch moves sata phy powerup from dedicate phy to compphy
and adds invert option for sata powerup routine.
Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90 Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53601 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: Igal Liberman <igall@marvell.com>
[a.heider: adapt to mainline] Signed-off-by: Andre Heider <a.heider@gmail.com> Tested-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Chee Hong Ang [Thu, 6 Aug 2020 03:56:29 +0000 (11:56 +0800)]
arm: socfpga: soc64: Check FPGA Config status register before bridge reset
Instead of querying SDM for FPGA configuration status through mailbox
messages, U-Boot now checks System Manager's FPGA Config status register
for FPGA configuration status before resetting bridge.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Gary Bisson [Thu, 27 Aug 2020 08:51:14 +0000 (10:51 +0200)]
fastboot: getvar: fix partition-size return value
The size returned by 'getvar partition-size' should be in bytes, not in
blocks as fastboot uses that value to generate empty partition when
running format [1].
Note that the function was already returning the proper size in bytes
for NAND devices (see struct part_info details).
yurii.pidhornyi [Thu, 20 Aug 2020 15:41:18 +0000 (18:41 +0300)]
fastboot: Fix fastboot reboot fail by changing functions order
It was revealed that when the fastboot_tx_write_str function is called
without the previously initialized fastboot_func->in_req->complete field,
a copy of in_req will be sent to the I/O requests queue without
an initialized field.
Moving a piece of code with the initializing of the
fastboot_func->in_req->complete field above transmit_tx allows to solve
this problem.
Fixes: 65c96757fe9 "usb: fastboot: Convert USB f_fastboot to shared fastboot" Signed-off-by: yurii.pidhornyi <yurii.pidhornyi@globallogic.com>
Sherry Sun [Tue, 18 Aug 2020 10:16:49 +0000 (18:16 +0800)]
f_sdp: Change bInterval of interrupt endpoint to 3
Since the USB HID limits the maximum bandwidth(3072) for interrupt
endpoint transfers, when the bInterval set to 1, we can only support 3
boards to run sdp at the same time. In order to support more boards,
change the bInterval of interrupt endpoint to 3, which will not affect
the transmission speed.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sherry Sun [Tue, 18 Aug 2020 10:16:48 +0000 (18:16 +0800)]
f_sdp: Add EP1_OUT as default data receive pipe in sdp
EP0 has been used to transfer file data in sdp before, but the max
packetsize of ep0 is 64 bytes. So in order to improve the file transfer
speed, here add the EP1_OUT interrupt endpoint which max packetsize is
set to 1024 byte.
After testing, it turns out that using ep1out is twice as fast as using
ep0 while receiving data in sdp.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 18 Aug 2020 10:16:46 +0000 (18:16 +0800)]
f_sdp: Support searching and loading FIT or container image
Add support to f_sdp to search and load iMX8 container image or iMX8M
FIT image by new UUU command SDPV.
When using the SDPV, the uuu will continue to send out data after first
level boot loader used by ROM. This means uuu won't skip to the offset
of the second boot loader, and the padding data before second boot loader
will be sent out. So we have to search the FIT header or container header
in the buffer that SDP received.
Also change to more common method to exit f_sdp handler not depending on
SPL_FIT_FOUND flag because container loader won't set this.
MAX3420 implements FullSpeed USB Device over SPI.
Another version MAX3421, also implements USB Host mode.
This driver should be good for the device mode of max3421 as well.
Default implementation of fastboot_set_reboot_flag function that depends
on "bcb" commands could be used in general case if there are no need to
make any platform-specific implementation, otherwise it could be
disabled via Kconfig option FASTBOOT_USE_BCB_SET_REBOOT_FLAG.
Please note that FASTBOOT_USE_BCB_SET_REBOOT_FLAG is mutually exclusive
with some platforms which already have their own implementation of this
function.
Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com>
fastboot: Add support for 'reboot fastboot' command
Android 10 adds support for dynamic partitions and in order to support
this userspace fastboot must be used[1]. New tool fastbootd is
included into recovery.
Userspace fastboot works from recovery and is launched if:
1) - Dynamic partitioning is enabled
2) - Boot control block has 'boot-fastboot' value into command field
The bootloader is expected to load and boot into the recovery image
upon seeing boot-fastboot in the BCB command. Recovery then parses the
BCB message and switches to fastbootd mode[2].
Please note that boot script is expected to handle 'boot-fastboot'
command in BCB and load into recovery mode.
Bootloader must support 'reboot fastboot' command which should reboot
device into userspace fastboot to accomodate those changes[3].
Another command that bootloader must support[3] is 'reboot recovery'. This
command should simply reboot device into recovery mode.
Signed-off-by: Roman Kovalivskyi <roman.kovalivskyi@globallogic.com> Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Change-Id: I9d2bdc9a6f6f31ea98572fe155e1cc8341e9af76
The environment variable loadaddr is in the virtual address space of the
sandbox. To get the actual memory address where the FIT image has been
loaded we have to convert this address according to the memory mapping of
the sandbox.
Equally the addresses in the *.its file have to be converted when used in
the dfu_ram driver.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Filip Brozovic [Mon, 29 Jun 2020 11:14:37 +0000 (13:14 +0200)]
fastboot: Support defining raw partitions without a partition table
Add support for defining raw fastboot partitions in eMMC by specifying
the offset and size in an environment variable. Optionally, the eMMC
hardware partition number may also be specified.
This makes it possible to e.g. update only part of the eMMC boot
partition, instead of having to write the entire partition.
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
Ye Li [Mon, 29 Jun 2020 02:12:26 +0000 (10:12 +0800)]
usb: gadget: Fix controller index in UMS
The usb mass storage (f_mass_storage.c) uses fixed usb index 0,
this causes problem while CDNS3 USB controller index is 1.
Modify the API of fsg to pass the controller index.
Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Hayes Wang [Tue, 16 Jun 2020 09:09:46 +0000 (17:09 +0800)]
eth/r8152: modify rtl_clear_bp function
The original rtl_clear_bp() is used to clear the firmware of both
PLA and USB MCU. The new one could clear the firmware of PLA or
USB independently. It is unnecessary to clear firmware, if there
is no one to be updated.
Besides, clear the firmware by writing the relative registers in
bulk.
Hayes Wang [Tue, 16 Jun 2020 09:09:44 +0000 (17:09 +0800)]
eth/r8152: reset bmu after disabling Tx/Rx
Reset bmu after disabling Tx/Rx. This is used to clear the FIFO of
Tx/Rx. The remained data may be transferred after Tx/Rx is re-enabled.
And it results in garbage data.
Marek Vasut [Sat, 9 May 2020 20:30:05 +0000 (22:30 +0200)]
serial: sh: Improve FIFO empty check on RX
If the SCIF is receiving data quickly enough, it may happen that the
SCxSR_RDxF flag is cleared in sh_serial_getc_generic(), while the
FIFO still contains data. If that happens, the serial_getc_check()
reports no data in the FIFO as the flag is no longer set. Add one
more check, if the SCxSR_RDxF is not set, read out the FIFO level
and if there are still characters in the FIFO, permit reading them
out.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Simon Glass [Sat, 29 Aug 2020 21:23:06 +0000 (15:23 -0600)]
x86: pinctrl: Fix 'relatove' typo
Fix this typo in the Kconfig help.
Suggested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Tue, 1 Sep 2020 08:33:52 +0000 (11:33 +0300)]
x86: qemu: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply replace the rule in it. We use stub C-file
like it's done for other boards.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:33 +0000 (13:02 +0300)]
x86: intel: slimbootloader: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:32 +0000 (13:02 +0300)]
x86: intel: minnowmax: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:31 +0000 (13:02 +0300)]
x86: intel: galileo: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:30 +0000 (13:02 +0300)]
x86: intel: edison: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:29 +0000 (13:02 +0300)]
x86: intel: crownbay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:28 +0000 (13:02 +0300)]
x86: intel: cougarcanyon2: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:27 +0000 (13:02 +0300)]
x86: intel: cherryhill: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:26 +0000 (13:02 +0300)]
x86: intel: bayleybay: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:25 +0000 (13:02 +0300)]
x86: efi: efi-x86_payload: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:23 +0000 (13:02 +0300)]
x86: coreboot: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:21 +0000 (13:02 +0300)]
x86: advantech: som-db5800-som-6867: Remove dead code
start.S does nothing and can be safely removed. Makefile is still being used
by the build system, so simply drop the rule from it.
Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 20 Aug 2020 10:02:20 +0000 (13:02 +0300)]
x86: Introduce USE_EARLY_BOARD_INIT option
Introduce USE_EARLY_BOARD_INIT option and select it by the actual users.
Cc: George McCollister <george.mccollister@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Wolfgang Wallner [Fri, 14 Aug 2020 07:55:24 +0000 (09:55 +0200)]
x86: mtrr: Fix parsing of "mtrr list" command
The command 'mtrr' does not recognize the 'list' subcommand any more
since the code restructuring in commit b2a76b3fe75a ("x86: mtrr:
Restructure so command execution is in one place").
The if-else parsing the command arguments does not take 'list' into
account: the if-branch is intended for no subcommands, the else-branch
is intended for the non-list subcommands (which all expect additional
arguments). Calling the 'mtrr list' subcommand leads to a "return
CMD_RET_USAGE" in the else-branch.
Fix this by changing the else-branch to explicitly checking for
if (cmd != 'l').
Fixes: b2a76b3fe75a ("x86: mtrr: Restructure so command execution is in one place") Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
- MVEBU Espressobin fixes and enhancements (fix switch security
issue, enable MVNETA, enable SD-card, fix COMPHY nodes, default
env variables, etc)
- MMC Xenon: Set signal voltage and max base clock
- a37xx PCI driver: Depend on DM_GPIO and remove #ifdef's
Pali Rohár [Thu, 27 Aug 2020 13:01:27 +0000 (15:01 +0200)]
arm: mvebu: Espressobin: Define fdt_addr and kernel_addr env aliases
Boot scripts for existing Espressobin Linux distributions, like OpenWRT,
expect that U-Boot set fdt_addr and kernel_addr envs. So add env aliases
from fdt_addr_r and kernel_addr_r values.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
Pali Rohár [Thu, 27 Aug 2020 13:01:26 +0000 (15:01 +0200)]
arm: mvebu: Espressobin: Change default loadaddr
Current loadaddr is not writable on Espressobin and 'loadb' command cause
rebooting board. Marvell's U-Boot already set default loadaddr to value
0x06000000 [1] and after this change 'loadb' is working fine.
Pali Rohár [Thu, 27 Aug 2020 13:01:25 +0000 (15:01 +0200)]
arm: mvebu: Espressobin: Move env load addresses
According to Marvell's U-Boot description [1] current env load addresses
overlaps with ATF RT services region and TEE. Because the ATF RT service
and TEE region is going to be marked as secure and can't be overwritten,
use different different addresses for envs.
Pali Rohár [Wed, 19 Aug 2020 14:24:17 +0000 (16:24 +0200)]
arm: mvebu: Espressobin: Setup MTD partitions when booting kernel
Due to different partition layouts in different U-Boot versions, DTS for
Espressobin in Linux does not contain any definition of MTD partitions.
See commit https://git.kernel.org/stable/c/00954566464a4 for more details.
This patch via ft_board_setup() hook fills current partition layout used by
U-Boot, so booted kernel would see correct MTD partitions layout.
U-Boot env partition is calculated from CONFIG_ENV_OFFSET option.
First partition contains secure firmware, ARM trusted firmware and U-Boot
with checksums. So it is not possible to replace just one image (e.g.
U-Boot) without updating other parts where is stored checksum of U-Boot.
Therefore there is no extra partition defined for U-Boot and first
partition is called just 'firmware'.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
Pali Rohár [Wed, 19 Aug 2020 14:24:16 +0000 (16:24 +0200)]
arm: mvebu: Espressobin: Make SPI env offset compatible with Marvell's U-Boot
Espressobin board comes with Marvell's U-Boot version where U-Boot env is
stored in SPI at offset 0x3F0000. This patch changes env offset in
Espressobin defconfig file to match Marvell's U-Boot version.
Users who want to use previous or different env offset can still change it
in .config file when compiling U-Boot.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
Evan Wang [Wed, 19 Aug 2020 14:19:39 +0000 (16:19 +0200)]
mmc: xenon: set signal voltage and max base clock
- The SDIO signal voltage and max base clock frequency
setting are missing in driver, which causes SDIO
not working.
- The patch adds SDIO signal voltage switch support,
which is based on regulator-gpio of vqmmc-supply, and
sets the max base clock frequency.
- Fix the zero clock value in call to sdhci_setup_cfg()
function.
Change-Id: I79c8860c65b8db166f4f70db56ede4097f71f1fa Signed-off-by: Evan Wang <xswang@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/53589 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com>
[pali: Amended fixup patch] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
Pali Rohár [Wed, 19 Aug 2020 13:57:07 +0000 (15:57 +0200)]
arm64: a37xx: pci: Assert PERST# signal when unloading driver
This change ensures that PCIe card is put into reset state when U-Boot
stops using it.
DM_FLAG_OS_PREPARE ensures that U-Boot executes driver's remove callback
prior booting Linux kernel.
Linux kernel pci-aardvark driver needs to reset PCIe card via PERST# signal
prior initializing it. If it does not issue reset then some PCIe cards
(specially Compex WiFi cards) are not detected at all.
Putting PCIe card into reset state prior booting Linux kernel would ensure
that card would be properly reset at time when Linux kernel starts
initializing pci-aardvark driver.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
Pali Rohár [Wed, 19 Aug 2020 13:57:06 +0000 (15:57 +0200)]
arm64: a37xx: pci: Make PCIe Reset GPIO DT compatible with Linux kernel DT
Change active-high to active-low and change DT property name from
reset-gpio to reset-gpios. This format of gpio reset is used by
pci-aardvark driver in Linux kernel.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Konstantin Porotchkin <kostap@marvell.com> Tested-by: Andre Heider <a.heider@gmail.com>
This commit fixes initialization of COMPHY on EspressoBin.
Commit 22f418935be4 ("phy: marvell: a3700: Use comphy_mux on Armada
37xx.") introduced usage of comphy_mux on Armada 37xx comphy driver.
The lanes are defined in comphy_a3700.c as described in functional
specification, that is:
lane 0 is SGMII1 or USB3
lane 1 is PCIe or SGMII0
lane 2 is SATA or USB3
But the DTS for EspressoBin configures PCIe on lane 0 and USB3 on
lane 1, which is wrong in the sense of the specification and doesn't
work with the comphy_mux code, which is 2 years now (the aardvark driver
causes synchronous abort in U-Boot).
It worked till the above mentioned commit, because the code for powering
up PCIe PHY doesn't work with lane number at all, and the code for
powering up USB3 PHY works differently only if USB3 is on lane 2, ie.
the check goes like:
if (lane == 2)
something
else
something else
so it does not differentiate between lanes 0 and 1.
In the future I shall post patches that remove the comphy_a3700 driver
and add comphy driver which uses calls to ATF, like Linux' driver does.
This will have the advantage of same DTS bindings as Linux', but till
this is done, we need this patch.
Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Pali Rohár <pali@kernel.org> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Andre Heider <a.heider@gmail.com>
Pali Rohár [Mon, 17 Aug 2020 14:36:38 +0000 (16:36 +0200)]
arm: mvebu: Espressobin: Disallow forwarding packets between wan and lan ports
By default Topaz switch on Espressobin board forwards packets between all
ethernet ports, including CPU (port 0), wan (port 1) and lan (ports 2,3).
This default U-Boot setup is unsuitable for using Espressobin as router as
it opens security hole in forwarding all packets between wan and lan ports.
E.g. dhcp packets from wan network leaks to lan network during small time
window until U-Boot boots Linux kernel which loads network drivers which
disallows forwarding between wan and lan.
This patch fixes above problem. For Espressobin board prior putting Topaz
switch into forwarding mode, Topaz switch is reconfigured to allow
forwarding packets from wan and lan ports only to CPU port. This ensures
that packets from wan port are not forwarded to lan ports and vice-versa.
Packets from CPU port are still forwarded to all other ports, so U-Boot
network boot works with any ethernet port as before.
This problem was already discussed on Espressobin forum [1] and on
Marvell's github issue tracker [2]. As a workaround people on Espressobin
forum patched U-Boot to completely disable lan ports on Topaz switch which
prevented forwarding packets. That workaround had an issue that U-Boot was
unable to netboot via lan ports anymore. Change in this patch does not have
such issue.
This security issue has been dicussed here as well: [3].
Michal Simek [Thu, 27 Aug 2020 13:43:48 +0000 (15:43 +0200)]
ti: common: Remove additional i2c read for board detection
There shouldn't be a need to call additional i2c read if above failed
already. Based on comment it should be enough to try to detect legacy
boards which are mentioned in the comment.
Fixes: 2463f6728e82 ("ti: common: board_detect: Allow DM I2C without CONFIG_DM_I2C_COMPAT") Fixes: 0bea813d0018 ("ARM: omap-common: Add standard access for board description EEPROM") Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / u-boot.git / log
