Ryder Lee [Thu, 15 Nov 2018 02:08:02 +0000 (10:08 +0800)]
serial: MediaTek: add high-speed uart driver for MediaTek SoCs
Many SoCs from MediaTek have a high-speed uart. This UART is compatible
with the ns16550 in legacy mode. It has extra registers for high-speed
mode which can reach a maximum baudrate at 921600.
However this UART will no longer be compatible if it's in high-speed mode.
Some BootROM of MediaTek's SoCs will change the UART into high-speed mode
and the U-Boot must use this driver to initialize the UART.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:08:00 +0000 (10:08 +0800)]
power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:07:58 +0000 (10:07 +0800)]
pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:07:54 +0000 (10:07 +0800)]
clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:07:51 +0000 (10:07 +0800)]
arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marcin Niestroj [Wed, 21 Nov 2018 19:32:02 +0000 (20:32 +0100)]
ARM: chiliboard: move towards driver model and device-tree boot
This patch mostly enables DM drivers in board defconfig and all their
dependencies. Additionally we remove ethernet platform data, as all
details are in device-tree now.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Otavio Salvador [Tue, 20 Nov 2018 18:47:12 +0000 (16:47 -0200)]
ARM: vexpress_*_defconfig: Enable CMD_UBI support
This allow for convenient use of QEMU machine to test loading of UBI
filesystem. There are a couple of changes made together of this which
are required:
1) The malloc must be at least 512 KiB to allow the use of UBI
filesystem. We are going to enable it in a next patch.
2) MTD_DEVICE must be enabled, otherwise we get missing symbols
during the build
Adam Ford [Tue, 20 Nov 2018 14:43:13 +0000 (08:43 -0600)]
board: da8xxevm: Fix Environmental CRC error
When the spi_flash_probe_bus_cs() was previously called, it was
called using 0's for two values where CONFIG_ENV_SPI_MAX_HZ and
CONFIG_ENV_SPI_MODE are now used. When changed this
caused the environment to fail the CRC check and the default
was used. This patch defines both of these values back 0.
Fixes: 25a17652c9c2 ("fix: env: Fix the SPI flash device setup
for DM mode")
Andrew F. Davis [Mon, 19 Nov 2018 20:47:53 +0000 (14:47 -0600)]
ARM: armv7: Add early stack for erratum workarounds
Some erratum workarounds call into C code before the stack
is setup, this can lead to values pushed onto the stack
being lost, firewall exceptions, and other undefined behavior.
Setup a temporary stack to allow these functions to work
correctly.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
Recent removal of obsolete partition led to shifting of starting address
of "reserved" partition (which reflects U-Boot environment). Fix its
start address to keep it in sync with ENV_OFFSET and DFU environment.
This patch also provides fixed start address for "reserved" partition,
so that we can track when it's shifted next time.
While at it, move it before "misc" partition to keep all Android
partitions together.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-By: Praneeth Bajjuri <praneeth@ti.com>
Lokesh Vutla [Thu, 15 Nov 2018 05:34:50 +0000 (11:04 +0530)]
armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.
If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
with this patch the selected Entry in bootmenu can be set by
environment-var bootmenu_default=<number> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This fixes link issues when building the SPL without USB driver model
but with USB storage support. CONFIG_BLK can be enabled and disabled
independently for SPL and non-SPL builds. We leverage that existing
functionality here.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Sven Schwermer [Wed, 21 Nov 2018 07:43:56 +0000 (08:43 +0100)]
usb: s/CONFIG_DM_USB/CONFIG_IS_ENABLED(DM_USB)/
This allows to disable the USB driver model in SPL because it checks
the CONFIG_SPL_DM_USB variable for SPL builds. Nothing changes for
regular non-SPL builds.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Sven Schwermer [Wed, 21 Nov 2018 07:43:55 +0000 (08:43 +0100)]
usb: Remove CMD_USB dependency for common code
Common USB code is built whenever USB is enabled (in non-SPL builds).
The USB uclass is built whenever (SPL_)DM_USB is enabled. Both need to
be independent from CMD_USB.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Sven Schwermer [Wed, 21 Nov 2018 07:43:53 +0000 (08:43 +0100)]
usb: Introduce CONFIG_SPL_DM_USB
This allows building the SPL without driver model for USB. Since
CONFIG_SPL_DM_USB is enabled if and only if CONFIG_DM_USB was enabled
before, this patch does not change the build behaviour.
Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Simon Glass [Fri, 16 Nov 2018 01:44:09 +0000 (18:44 -0700)]
spl: Add support for passing handoff info to U-Boot proper
There is some basic informaton that SPL normally wants to pass through to
U-Boot, such as the SDRAM size and bank information.
Mkae use of the new bloblist structure for this. Add a new 'handoff' blob
which is set up in SPL and passed to U-Boot proper. Also adda test for
sandbox_spl that checks that this works correctly and a new 'sb' command
to show the information passed from SPL.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 16 Nov 2018 01:44:08 +0000 (18:44 -0700)]
sandbox: Boot in U-Boot through the standard call
Most architectures use jump_to_image_no_args() to jump from SPL to U-Boot.
At present sandbox is special in that it jumps in its
spl_board_load_image() call. This is not strictly correct, and means that
sandbox misses out some parts of board_init_r(), just as calling
bloblist_finish(), for example.
Change spl_board_load_image() to just identify the filename to boot, and
implement jump_to_image_no_args() to actually jump to it.
Simon Glass [Fri, 16 Nov 2018 01:44:07 +0000 (18:44 -0700)]
sandbox: Filter arguments when starting U-Boot
The current method of starting U-Boot from U-Boot adds arguments to pass
the memory file through, so that memory is preserved. This is fine for a
single call, but if we call from TPL -> SPL -> U-Boot the arguments build
up and we have several memory files in the argument list.
Adjust the implementation to filter out arguments that we want to replace
with new ones. Also print a useful error if the exec() call fails.
Simon Glass [Fri, 16 Nov 2018 01:44:06 +0000 (18:44 -0700)]
sandbox: Use malloc() and free() from os layer
At present sandbox calls malloc() from various places in the OS layer and
this results in calls to U-Boot's malloc() implementation. It is better to
use the on in the OS layer, since it does not mix allocations with the
main U-Boot code.
Fix this by replacing calls with malloc() to os_malloc(), etc.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Fri, 16 Nov 2018 01:44:04 +0000 (18:44 -0700)]
sandbox: Allow puts() output before global_data is set up
We support putc() in this case but not puts(), but this is more useful
since it is what printf() uses.
This particularly affects debugging early in SPL, where currently printf()
statements result in no output. Fix this by adding a special case into
puts() for sandbox, just like putc().
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Fri, 16 Nov 2018 01:44:03 +0000 (18:44 -0700)]
sandbox: Add a new 'sb' command
The old 'sb' command was deprecated in 2015 and replaced with 'host'. It
is useful to be able to access some internal sandbox state, particularly
for testing.
Resurrect the old command and provide a way to print some basic state
information (currently just the arguments to sandbox).
Simon Glass [Fri, 16 Nov 2018 01:44:02 +0000 (18:44 -0700)]
sandbox: Drop the deprecated 'sb' command
The old 'sb' command was deprecated in 2015 and replaced with 'host'.
Remove the remaining users and the command, so that the name is available
for other purposes.
Simon Glass [Fri, 16 Nov 2018 01:44:00 +0000 (18:44 -0700)]
test/py: Add a way to pass flags to sandbox
It is sometimes useful to restart sandbox with some particular flags to
test certain functionality. Add a new method to ConsoleSandbox to handle
this, without changing the existing APIs.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Fri, 16 Nov 2018 01:43:58 +0000 (18:43 -0700)]
spl: Add a comment to spl_set_bd()
There is a strange feature to set global_data to a data-section variable
early in SPL. This only works if SPL actually has access to SRAM which is
not the case on x86, for eaxmple. Add a comment to this effect.
Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 16 Nov 2018 01:43:56 +0000 (18:43 -0700)]
spl: Add a define for SPL_TPL_PROMPT
We should use a macro rather than hard-coding the SPL prompt to 'spl'
since the code can be used by TPL too. Add a macro that works for both
and use it in various places.
This allows TPL to use the same code without printing confusing messages.
Note that the string is lower case ('spl', 'tpl') which is a change from
previously.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 16 Nov 2018 01:43:55 +0000 (18:43 -0700)]
spl: Support hash, input, pch, pci, rtc, tpm in SPL
At present these subsystems are only supported in U-Boot proper but it is
sometimes necessary to support them in SPL, or even TPL. Update the
Kconfig and Makefile to support this. Also adjust GPIO so that it can be
used in TPL if required.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Fri, 16 Nov 2018 01:43:50 +0000 (18:43 -0700)]
Add core support for a bloblist to convey data from SPL
At present there is no standard way in U-Boot to pass information from SPL
to U-Boot proper. But sometimes SPL wants to convey information to U-Boot
that U-Boot cannot easily figure out. For example, if SPL sets up SDRAM
then it might want to pass the size of SDRAM, or the location of each
bank, to U-Boot proper.
Add a new 'bloblist' feature which provides this. A bloblist is set up in
the first phase of U-Boot that runs (i.e. TPL or SPL). The location of
this info may be in SRAM or CAR (x86 cache-as-RAM) or somewhere else.
Information placed in this region is preserved (with a checksum) through
TPL and SPL and ends up in U-Boot. At this point it is copied into SDRAM
so it can be used after relocation.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com>
AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.
This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.
This approach also provide the expansion when the
vender specific features are going to join in.
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
Rick Chen [Tue, 13 Nov 2018 07:13:34 +0000 (15:13 +0800)]
riscv: dts: Sync to Linux Kernel ae350 dts.
Use same dts to boot U-Boot and Kernel.
Following are the change notes :
1 Remove early printk bootargs.
2 Timer frequency are changed to 60MHz.
3 Add dma, snd, lcd, virtio nodes which are used
in kernel drivers. They does not been used by U-Boot.
4 Change spi irq from 3 to 4.
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:37 +0000 (11:26 +0100)]
riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
QEMU specifies the location of Linux (supplied with the -kernel
argument) in the device tree using the riscv,kernel-start and
riscv,kernel-end properties. We currently rely on the SBI implementation
of BBL to run Linux and therefore embed Linux as payload in BBL. This
causes an issue, because BBL detects the kernel properties in the device
tree and ignores the Linux payload as a result.
Work around this issue by clearing the kernel properties in the device
tree before booting Linux.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:36 +0000 (11:26 +0100)]
riscv: qemu: detect and boot the kernel passed by QEMU
QEMU embeds the location of the kernel image in the device tree. Store
this address in the environment as variable kernel_start. It is used in
the board-local distro boot command QEMU to boot the kernel with the
U-Boot device tree. The QEMU boot command is added as the first boot
target device.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
Lukas Auer [Thu, 22 Nov 2018 10:26:32 +0000 (11:26 +0100)]
riscv: align bootm implementation with that of other architectures
The bootm implementation of RISC-V diverges from that of other
architectures. Update it to match the implementation of other
architectures. The ARM implementation is used as a reference.
This adds the following features and changes to RISC-V.
* Add support for the BOOTM_STATE_OS_FAKE_GO command
* Call the remove function on devices with the removal flag set before
booting Linux
* Force disconnect USB devices from the host before booting Linux
* Print and add bootstage information to the device tree before booting
Linux
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:31 +0000 (11:26 +0100)]
riscv: qemu: support booting Linux
Support booting Linux (as payload of BBL) from FIT images. For this, the
default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment
variables fdt_high and initrd_high are set to mark the device tree and
initrd as in-place.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:30 +0000 (11:26 +0100)]
riscv: qemu: use device tree passed by prior boot stage
QEMU provides a device tree, which is passed to U-Boot using register
a1. We are now able to directly select the device tree with the
configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in
qemu-riscv with it.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:29 +0000 (11:26 +0100)]
riscv: save hart ID and device tree passed by prior boot stage
Store the hart ID and device tree passed by the prior boot stage (in a0
and a1) in registers s0 and s1. Replace one use of s1 in start.S to
avoid overwriting it.
The device tree is also stored in memory to make it available to U-Boot
with the configuration CONFIG_OF_PRIOR_STAGE.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:28 +0000 (11:26 +0100)]
riscv: do not blindly modify the mstatus CSR
The mstatus CSR includes WPRI (writes preserve values, reads ignore
values) fields and must therefore not be set to zero without preserving
these fields. It is not apparent why mstatus is set to zero here since
it is not required for U-Boot to run. Remove it.
This instruction and others encode zero as an immediate. RISC-V has the
zero register for this purpose. Replace the immediates with the zero
register.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:23 +0000 (11:26 +0100)]
riscv: implement the invalidate_icache_* functions
Implement the functions invalidate_icache_range() and
invalidate_icache_all().
RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:18 +0000 (11:26 +0100)]
riscv: make use of the barrier functions from Linux
Replace the barrier functions in arch/riscv/include/asm/io.h with those
defined in barrier.h, which is imported from Linux. This version is
modified to remove the include statement of asm-generic/barrier.h, which
is not available in U-Boot or required.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:17 +0000 (11:26 +0100)]
riscv: fix use of incorrectly sized variables
The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in
several places. Fix this.
In addition, BITS_PER_LONG is set to 64 on RV64I systems.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:15 +0000 (11:26 +0100)]
riscv: set -march and -mabi based on the Kconfig configuration
Use the new Kconfig entries to construct the ISA string for the -march
compiler flag. The -mabi compiler flag is selected based on the base
integer instruction set.
With this change, the C (compressed instructions) ISA extension is now
enabled for all boards with CONFIG_RISCV_ISA_C set. Buildman reports a
decrease in binary size of 71590 bytes.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:14 +0000 (11:26 +0100)]
riscv: add Kconfig entries for the C and A ISA extensions
Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.
The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Lukas Auer [Thu, 22 Nov 2018 10:26:12 +0000 (11:26 +0100)]
riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Icenowy Zheng [Thu, 22 Nov 2018 23:37:48 +0000 (00:37 +0100)]
sun8i_emac: add support for setting EMAC TX/RX delay
Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.
This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.
Add support for setting these delays.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
sunxi-mmc: don't double clock for new mode unconditionally
Comment in Linux driver says that clock needs to be doubled only
if we use DDR modes, moreover divider has to be set accordingly.
U-boot driver doesn't declare support for any DDR modes and doesn't
set internal clock divider in CLKCR, so it doubles clock
unconditionally when new mode is used.
Some cards can't handle that and as result SPL fails to load u-boot.
Fixes: de9b1771c3b ("mmc: sunxi: Support new mode") Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled
Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Simon Glass [Tue, 6 Nov 2018 22:21:41 +0000 (15:21 -0700)]
sf: Add a method to obtain the block-protect setting
It is useful to obtain the block-protect setting of the SPI flash, so we
know whether it is fully open or (perhaps partially) write-protected. Add
a method for this. Update the sandbox driver to process this operation and
add a test.
Simon Glass [Tue, 6 Nov 2018 22:21:40 +0000 (15:21 -0700)]
test: sf: Add a simple SPI flash test
The current test is a functional test, covering all the way from the
command line to the sandbox SPI driver. This is useful, but it is easier
to diagnose failures with a smaller test.
Add a simple test which reads and writes data and checks that it is stored
and retrieved correctly.
projects / u-boot.git / log
![6 years agoriscv: cache: Implement i/dcache [status, enable, disable]](/img/sics.gif?p=u-boot.git;a=commit;h=52923c6db7f00e0197ec894c8c1bb8a7681974bb){kind=link}
