Alison Wang [Wed, 4 Dec 2019 06:21:55 +0000 (06:21 +0000)]
configs: Enable SPL_FSL_PBL for some LayerScape platforms
In commit <db4080d56dec>, SPL_FSL_PBL is removed from the configs of
some LayerScape platforms. Actually, SPL_FSL_PBL is needed for SD/NAND
boot on LS1021A/LS1043A/LS1046A to create boot binary having SPL binary
in PBI format concatenated with u-boot binary. SPL_FRAMEWORK is used on
these platforms too.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Alex Marginean [Wed, 27 Nov 2019 15:19:32 +0000 (17:19 +0200)]
ls1028a: Configure stream IDs for integrated PCI and fix up Linux DT
Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Ran Wang [Tue, 26 Nov 2019 03:40:40 +0000 (11:40 +0800)]
armv8: Add workaround for USB erratum A-050106
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
and the register value is different.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
drivers/fsl-mc: Support DPSPARSER object and apply spb command
Add support for DPSPARSER object (create/destroy, open/close, apply spb)
which is required to configure Soft Parser by using MC.
Also add uboot command to apply Soft Parser Blob with command:
fsl_mc apply spb <spb_load_addr>
Tom Rini [Tue, 24 Dec 2019 13:18:19 +0000 (08:18 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx into next
- Enable DM driver on ppc/km boards
- Enable DM_USB for some of NXP powerpc platforms: P5040, T4240, T208x,
T104x, P4080, P2041, P2020, P1020, P3041
- Some updates in mpc85xx-ddr driver, km boards
Joakim Tjernlund [Wed, 27 Nov 2019 18:35:10 +0000 (19:35 +0100)]
mpc85xx: ddr: Always start DDR RAM in Self Refresh mode
Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Tom Rini [Wed, 18 Dec 2019 12:20:19 +0000 (07:20 -0500)]
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
Tom Rini [Tue, 17 Dec 2019 12:53:08 +0000 (07:53 -0500)]
Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next
- misc: i2c_eeprom:
Add partition support and add ability to query size
of eeprom device and partitions
- i2c common:
add support for offset overflow in to address and add
sandbox tests for it.
Robert Beckett [Mon, 28 Oct 2019 17:44:57 +0000 (17:44 +0000)]
i2c: add support for offset overflow in to address
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.
Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Ian Ray <ian.ray@ge.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Mon, 9 Dec 2019 00:40:20 +0000 (17:40 -0700)]
x86: Add chromebook_coral
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 9 Dec 2019 00:40:12 +0000 (17:40 -0700)]
spl: Add methods to find the position/size of next phase
Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.
Add functions to return these useful values, along with symbols to allow
TPL to load SPL.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 9 Dec 2019 00:40:09 +0000 (17:40 -0700)]
x86: apl: Add LPC driver
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Mon, 9 Dec 2019 00:40:08 +0000 (17:40 -0700)]
x86: apl: Add ITSS driver
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:58 +0000 (21:42 -0700)]
x86: apl: Add UART driver
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:54 +0000 (21:42 -0700)]
x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:53 +0000 (21:42 -0700)]
x86: Add a generic Intel pinctrl driver
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.
As well as a pinctrl driver this provides a GPIO driver based on the same
code.
Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:50 +0000 (21:42 -0700)]
mtd: spi: Export spi_flash_std_probe()
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.
To avoid duplicating the probing code, export this probe function for use
by these drivers.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:48 +0000 (21:42 -0700)]
spi: ich: Add TPL support
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:42 +0000 (21:42 -0700)]
spi: ich: Add mmio_base to struct ich_spi_platdata
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:41 +0000 (21:42 -0700)]
spi: ich: Various small tidy-ups
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:38 +0000 (21:42 -0700)]
spi: ich: Move the protection/lockdown code into a function
Reduce the size of the probe function but putting this code into its own
function.
Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:37 +0000 (21:42 -0700)]
spi: ich: Move init function just above probe()
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:36 +0000 (21:42 -0700)]
x86: spi: Don't enable SPI_FLASH_BAR by default
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.
Drop the default enabling of this option on x86.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:33 +0000 (21:42 -0700)]
x86: Separate out U-Boot and device tree in ROM image
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.
Do the same for SPL tool.
In both cases, group the two parts into a section so that SPL symbols get
the correct total size.
It may be possible for binman to handle this automatically at some point,
by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and
u-boot.dtb
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:32 +0000 (21:42 -0700)]
x86: Don't repeat microcode in U-Boot if not needed
At present if SPL sets up the microcode then it is still included in
U-Boot as well. This is wasteful as microcode is large. Adjust the logic
in the image to prevent this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:31 +0000 (21:42 -0700)]
x86: Add an fdtmap and image-header
Add these entries to the ROM so that we can list the contents of an image
with 'binman ls'. The image-header is not essential but does speed up
access.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:30 +0000 (21:42 -0700)]
x86: Add an option to control the position of SPL
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).
Add a Kconfig option for the ROM position.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 7 Dec 2019 04:42:26 +0000 (21:42 -0700)]
x86: Disable microcode section for FSP2
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
projects / u-boot.git / log
