]> git.dujemihanovic.xyz Git - u-boot.git/log
u-boot.git
3 years agoMIPS: malta: enable PCI driver model
Daniel Schwierzeck [Thu, 15 Jul 2021 18:54:01 +0000 (20:54 +0200)]
MIPS: malta: enable PCI driver model

Enable DM_PCI and DM_ETH on MIPS Malta.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agoMIPS: malta: add support for PCI driver model
Daniel Schwierzeck [Thu, 15 Jul 2021 18:54:00 +0000 (20:54 +0200)]
MIPS: malta: add support for PCI driver model

As almost all peripherals are connected via PCI dependent on the
used core card, PCI setup is always required. Thus run pci_init()
including PCI scanning and probing and core card specific setups
in board_early_init_r().

Also prepare support for dynamically managing the status of the
different PCI DT nodes dependent on used core card via option
CONFIG_OF_BOARD_FIXUP. Before this feature can be enabled,
the call order of the fix_fdt() init hook in board_init_f
needs to be changed. Otherwise rw_fdt_blob points to a read-only
NOR flash address. Thus this options needs to stay disabled
until the board_init_f problem could be solved. This breaks
running the default U-Boot image on real HW using the FPGA core
card but Qemu emulation still works. Currently Qemu is more
important as MIPS CI tests depend on Malta and the deadline
for PCI DM conversion will be enforced soon.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agoMIPS: malta: add DT bindings for PCI host controller
Daniel Schwierzeck [Thu, 15 Jul 2021 18:53:59 +0000 (20:53 +0200)]
MIPS: malta: add DT bindings for PCI host controller

Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 years agopci: msc01: convert to driver model
Daniel Schwierzeck [Thu, 15 Jul 2021 18:53:58 +0000 (20:53 +0200)]
pci: msc01: convert to driver model

This driver is currently only used on MIPS Malta boards.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agopci: gt64120: convert to driver model
Daniel Schwierzeck [Thu, 15 Jul 2021 18:53:57 +0000 (20:53 +0200)]
pci: gt64120: convert to driver model

This driver is currently only used on MIPS Malta boards.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agodm: pci: add option to map virtual system memory base address
Daniel Schwierzeck [Thu, 15 Jul 2021 18:53:56 +0000 (20:53 +0200)]
dm: pci: add option to map virtual system memory base address

On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.

Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agomips: mt7688: gardena-smart-gateway: Adjust to production values
Reto Schneider [Thu, 17 Jun 2021 16:09:34 +0000 (18:09 +0200)]
mips: mt7688: gardena-smart-gateway: Adjust to production values

This commit updates the default config with the values that will
be used soon on the MediaTek MT7688 based GARDENA smart gateway.

CONFIG_SPL_SYS_MALLOC_F_LEN had to be increased due to the more
demanding new configuration.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoMerge branch '2021-07-16-cleanup-image-support'
Tom Rini [Sat, 17 Jul 2021 15:39:50 +0000 (11:39 -0400)]
Merge branch '2021-07-16-cleanup-image-support'

- A large rework of the logic around supporting various image
  types/formats and sharing between the host and target.

3 years agoMerge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Tom Rini [Sat, 17 Jul 2021 14:52:21 +0000 (10:52 -0400)]
Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277

3 years agomx7ulp: wdog: Wait for WDOG unlock and reconfiguration to complete
Breno Lima [Tue, 29 Jun 2021 02:32:35 +0000 (10:32 +0800)]
mx7ulp: wdog: Wait for WDOG unlock and reconfiguration to complete

According to i.MX7ULP Reference Manual we should wait for WDOG unlock
and reconfiguration to complete.

Section "59.5.3 Configure Watchdog" provides the following example:

DisableInterrupts; //disable global interrupt
WDOG_CNT = 0xD928C520; //unlock watchdog
while(WDOG_CS[ULK]==0); //wait until registers are unlocked
WDOG_TOVAL = 256; //set timeout value
WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) |
  WDOG_CS_WIN(0) | WDOG_CS_UPDATE(1);
while(WDOG_CS[RCS]==0); //wait until new configuration takes effect
EnableInterrupts; //enable global interrupt

Update U-Boot WDOG driver to align with i.MX7ULP reference manual.

Use 32 bits accessing to CS register. According to RM, the bits in
this register only can write once after unlock. So using 8 bits access
will cause problem.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
3 years agomx7ulp: Update unlock and refresh sequences in sWDOG driver
Breno Lima [Tue, 29 Jun 2021 02:32:34 +0000 (10:32 +0800)]
mx7ulp: Update unlock and refresh sequences in sWDOG driver

According to i.MX7ULP Reference Manual the second word write for both
UNLOCK and REFRESH operations must occur in maximum 16 bus clock.

The current code is using writel() function which has a DMB barrier to
order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing a WDOG timeout due to 16 bus
clock window requirement.

Replace writel() function by __raw_writel() to achieve a faster memory
access and avoid such issue.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
3 years agoimx8mq_evk: Enable the USB3.0 host port
Ye Li [Sun, 21 Feb 2021 16:26:24 +0000 (08:26 -0800)]
imx8mq_evk: Enable the USB3.0 host port

Setup USB clock in board codes, and enable the DWC3 XHCI and
PHY drivers to make USB3.0 host port working on i.MX8MQ EVK.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
3 years agoarm: imx8mq: Add USB clock init function
Ye Li [Sun, 21 Feb 2021 16:26:23 +0000 (08:26 -0800)]
arm: imx8mq: Add USB clock init function

Add clock function to setup relevant clocks for USB3.0 controllers and
PHYs on i.MX8MQ

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
3 years agoarm: dts: imx8mq: Add alias for two usb controllers
Ye Li [Sun, 21 Feb 2021 16:26:22 +0000 (08:26 -0800)]
arm: dts: imx8mq: Add alias for two usb controllers

Add alias for two DWC3 usb controllers to fix the seq index.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Patrick Wildt <patrick@blueri.se>
3 years agophy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ
Ye Li [Sun, 21 Feb 2021 16:26:21 +0000 (08:26 -0800)]
phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ

Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
3 years agotools: Use a single target-independent config to enable OpenSSL
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:47 +0000 (17:05 -0500)]
tools: Use a single target-independent config to enable OpenSSL

Host tool features, such as mkimage's ability to sign FIT images were
enabled or disabled based on the target configuration. However, this
misses the point of a target-agnostic host tool.

A target's ability to verify FIT signatures is independent of
mkimage's ability to create those signatures. In fact, u-boot's build
system doesn't sign images. The target code can be successfully built
without relying on any ability to sign such code.

Conversely, mkimage's ability to sign images does not require that
those images will only work on targets which support FIT verification.
Linking mkimage cryptographic features to target support for FIT
verification is misguided.

Without loss of generality, we can say that host features are and
should be independent of target features.

While we prefer that a host tool always supports the same feature set,
we recognize the following
  - some users prefer to build u-boot without a dependency on OpenSSL.
  - some distros prefer to ship mkimage without linking to OpenSSL

To allow these use cases, introduce a host-only Kconfig which is used
to select or deselect libcrypto support. Some mkimage features or some
host tools might not be available, but this shouldn't affect the
u-boot build.

I also considered setting the default of this config based on
FIT_SIGNATURE. While it would preserve the old behaviour it's also
contrary to the goals of this change. I decided to enable it by
default, so that the default build yields the most feature-complete
mkimage.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Add support for relocating crypto_algos in linker lists
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:46 +0000 (17:05 -0500)]
image: Add support for relocating crypto_algos in linker lists

Function pointers from crypto_algos array are relocated, when
NEEDS_MANUAL_RELOC is set. This relocation doesn't happen if the algo
is placed in a linker list. Implement this relocation.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
3 years agoimage: Eliminate IMAGE_ENABLE_VERIFY_ECDSA macro
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:45 +0000 (17:05 -0500)]
image: Eliminate IMAGE_ENABLE_VERIFY_ECDSA macro

This macro is no longer needed for code flow or #ifdefs. Remove it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoimage: Eliminate IMAGE_ENABLE_VERIFY macro
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:44 +0000 (17:05 -0500)]
image: Eliminate IMAGE_ENABLE_VERIFY macro

This macro is no longer needed for code flow or #ifdefs. Remove it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agolib: rsa: Remove #ifdefs from rsa.h
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:43 +0000 (17:05 -0500)]
lib: rsa: Remove #ifdefs from rsa.h

It is no longer necessary to implement rsa_() functions as no-ops
depending on config options. It is merely sufficient to provide the
prototypes, as the rsa code is no longer linked when unused.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agolib: ecdsa: Remove #ifdefs from ecdsa.h
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:42 +0000 (17:05 -0500)]
lib: ecdsa: Remove #ifdefs from ecdsa.h

It is no longer necessary to implement ecdsa_() functions as no-ops
depending on config options. It is merely sufficient to provide the
prototypes, as the ecdsa code is no longer linked when unused.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoimage: image-sig.c: Remove crypto_algos array
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:41 +0000 (17:05 -0500)]
image: image-sig.c: Remove crypto_algos array

Crytographic algorithms (currently RSA), are stored in linker lists.
The crypto_algos array is unused, so remove it, and any logic
associated with it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoimage: rsa: Move verification algorithm to a linker list
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:40 +0000 (17:05 -0500)]
image: rsa: Move verification algorithm to a linker list

Move the RSA verification crytpo_algo structure out of the
crypto_algos array, and into a linker list.

Although it appears we are adding an #ifdef to rsa-verify.c, the gains
outweigh this small inconvenience. This is because rsa_verify() is
defined differently based on #ifdefs. This change allows us to have
a single definition of rsa_verify().

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoimage: Add support for placing crypto_algo in linker lists
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:39 +0000 (17:05 -0500)]
image: Add support for placing crypto_algo in linker lists

The purpose of this change is to enable crypto algorithms to be placed
in linker lists, rather than be declared as a static array. The goal
is to remove the crypto_algos array in a subsequent patch.

Create a new linker list named "cryptos", and search it when
image_get_crypto_algo() is invoked.

NOTE that adding support for manual relocation of crypto_algos within
linker lists is beyond the scope of this patch.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agocommon: image-sig.c: Remove host-specific logic and #ifdefs
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:38 +0000 (17:05 -0500)]
common: image-sig.c: Remove host-specific logic and #ifdefs

Remove any ifdefs in image-sig.c that were previously used to
differentiate from the host code. Note that all code dedicated to
relocating ->sign() and ->add_verify_data)_ can be safely removed,
as signing is not supported target-side.

NOTE that although it appears we are removing ecdsa256 support, this
is intentional. ecdsa_verify() is a no-op on the target, and is
currently only used by host code.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agocommon: Move host-only logic in image-sig.c to separate file
Alexandru Gagniuc [Wed, 14 Jul 2021 22:05:37 +0000 (17:05 -0500)]
common: Move host-only logic in image-sig.c to separate file

image-sig.c is used to map a hash or crypto algorithm name to a
handler of that algorithm. There is some similarity between the host
and target variants, with the differences worked out by #ifdefs. The
purpose of this change is to remove those ifdefs.

First, copy the file to a host-only version, and remove target
specific code. Although it looks like we are duplicating code,
subsequent patches will change the way target algorithms are searched.
Besides we are only duplicating three string to struct mapping
functions. This isn't something to fuss about.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
3 years agoimage: Drop IMAGE_ENABLE_BEST_MATCH
Simon Glass [Wed, 14 Jul 2021 22:05:36 +0000 (17:05 -0500)]
image: Drop IMAGE_ENABLE_BEST_MATCH

This is not needed with Kconfig, since we can use IS_ENABLED() easily
enough. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Drop IMAGE_ENABLE_SHAxxx
Simon Glass [Wed, 14 Jul 2021 22:05:35 +0000 (17:05 -0500)]
image: Drop IMAGE_ENABLE_SHAxxx

We already have a host Kconfig for these SHA options. Use
CONFIG_IS_ENABLED(SHAxxx) directly in the code shared with the host build,
so we can drop the unnecessary indirections.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Drop IMAGE_ENABLE_SHA1
Simon Glass [Wed, 14 Jul 2021 22:05:34 +0000 (17:05 -0500)]
image: Drop IMAGE_ENABLE_SHA1

We already have a host Kconfig for SHA1. Use CONFIG_IS_ENABLED(SHA1)
directly in the code shared with the host build, so we can drop the
unnecessary indirection.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoKconfig: Rename SPL_MD5_SUPPORT to SPL_MD5
Simon Glass [Wed, 14 Jul 2021 22:05:33 +0000 (17:05 -0500)]
Kconfig: Rename SPL_MD5_SUPPORT to SPL_MD5

Drop the _SUPPORT suffix so we can use CONFIG_IS_ENABLED() with this
option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoKconfig: Rename SPL_CRC32_SUPPORT to SPL_CRC32
Simon Glass [Wed, 14 Jul 2021 22:05:32 +0000 (17:05 -0500)]
Kconfig: Rename SPL_CRC32_SUPPORT to SPL_CRC32

Drop the _SUPPORT suffix so we can use CONFIG_IS_ENABLED() with this
option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Rename CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT
Simon Glass [Wed, 14 Jul 2021 22:05:31 +0000 (17:05 -0500)]
image: Rename CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT

Drop the ENABLE and SUPPORT parts of this, which are redundant.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Rename SPL_SHAxxx_SUPPORT to SPL_FIT_SHAxxx
Simon Glass [Wed, 14 Jul 2021 22:05:30 +0000 (17:05 -0500)]
image: Rename SPL_SHAxxx_SUPPORT to SPL_FIT_SHAxxx

These option are named inconsistently with other SPL options, thus making
them incompatible with the CONFIG_IS_ENABLED() macro. Rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoimage: Shorten FIT_ENABLE_SHAxxx_SUPPORT
Simon Glass [Wed, 14 Jul 2021 22:05:29 +0000 (17:05 -0500)]
image: Shorten FIT_ENABLE_SHAxxx_SUPPORT

The ENABLE part of this name is redundant, since all boolean Kconfig
options serve to enable something. The SUPPORT part is also redundant
since Kconfigs can be assumed to enable support for something. Together
they just serve to make these options overly long and inconsistent
with other options.

Rename FIT_ENABLE_SHAxxx_SUPPORT to FIT_SHAxxx

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
3 years agoMerge branch '2021-07-15-assorted-fixes'
Tom Rini [Fri, 16 Jul 2021 13:15:59 +0000 (09:15 -0400)]
Merge branch '2021-07-15-assorted-fixes'

- Large number of Coverity reported issues addressed
- m41t62 bugfix
- Support more Android image compression formats
- FIT + DTO bugfix

3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Fri, 16 Jul 2021 13:15:21 +0000 (09:15 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- designware_wdt: reset watchdog in designware_wdt_stop() function
  (Meng)
- socfpga_stratix10: enable wdt command (Meng)
- wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART (Teresa)

3 years agoMerge tag 'u-boot-stm32-20210715' of https://source.denx.de/u-boot/custodians/u-boot-stm
Tom Rini [Fri, 16 Jul 2021 13:15:05 +0000 (09:15 -0400)]
Merge tag 'u-boot-stm32-20210715' of https://source.denx.de/u-boot/custodians/u-boot-stm

- DTS: alignment with Linux kernel v5.13 for stm32mp15 boards
- STM32MP1: update the stm32key command
- STM32MP1: activate the rng command
- STM32MP1: fix the stm32prog command (help, parttition size)
- STM32MP1: add fdtoverlay_addr_r variable
- STM32MP1: correctly managed SYSCON/SYSCFG clock
- STM32MP1: remove mmc alias and directly use device instance in boot_instance variable

3 years agodrivers: watchdog: wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART
Teresa Remmet [Thu, 15 Jul 2021 11:26:32 +0000 (13:26 +0200)]
drivers: watchdog: wdt-uclass: Use IS_ENABLED for WATCHDOG_AUTOSTART

There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in SPL again.

Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting watchdog")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: socfpga: socfpga_stratix10: enable wdt command by default
MengLi [Mon, 24 May 2021 02:22:49 +0000 (10:22 +0800)]
arm: socfpga: socfpga_stratix10: enable wdt command by default

In latest u-boot code, watchdog feature is implemented, so enable
wdt command by default.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
3 years agodriver: watchdog: reset watchdog in designware_wdt_stop() function
MengLi [Mon, 24 May 2021 02:22:48 +0000 (10:22 +0800)]
driver: watchdog: reset watchdog in designware_wdt_stop() function

In uboot command line environment, watchdog is not able to be
stopped with below commands:
SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
SOCFPGA_STRATIX10 # wdt stop
Refer to watchdog driver in linux kernel, it is also need to reset
watchdog after disable it so that the disable action takes effect.

Signed-off-by: Meng Li <Meng.Li@windriver.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
3 years agoARM: dts: stm32mp15: remove mmc alias
Patrick Delaunay [Tue, 6 Jul 2021 15:19:46 +0000 (17:19 +0200)]
ARM: dts: stm32mp15: remove mmc alias

Remove the mmc alias no more required as the sequence number
of mmc device is used for boot_instance.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: use device sequence number in boot_instance variable
Patrick Delaunay [Tue, 6 Jul 2021 15:19:45 +0000 (17:19 +0200)]
stm32mp: use device sequence number in boot_instance variable

Use the device sequence number in boot_instance variable
and no more the SDMMC instance provided by ROM code/TF-A.

After this patch we don't need to define the mmc alias in
device tree, for example:
  mmc0 = &sdmmc1;
  mmc1 = &sdmmc2;
  mmc2 = &sdmmc3;
to have a correct mapping between the ROM code boot device =
"${boot_device}${boot_instance}" and the MMC device in U-Boot.

With this patch the 'mmc0' device (used in mmc commands) is
always used when only one instance sdmmc is activated in device
tree, even if it is only the sdmmc2 or sdmmc3.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: use defines for virtual partition size
Patrick Delaunay [Mon, 5 Jul 2021 07:39:01 +0000 (09:39 +0200)]
stm32mp: stm32prog: use defines for virtual partition size

Use the existing defines PMIC_SIZE and OTP_SIZE and a new define
CMD_SIZE for virtual partition size.

This patch corrects the size for OTP partition in alternate name
(1024 instead of 512) and avoids other alignment issues.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoconfigs: stm32mp1: activate command rng
Patrick Delaunay [Tue, 29 Jun 2021 10:08:27 +0000 (12:08 +0200)]
configs: stm32mp1: activate command rng

Activate the command rng with CONFIG_CMD_RNG, used to test
the rng driver

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: syscon: manage clock when present in device tree
Patrick Delaunay [Tue, 29 Jun 2021 10:04:23 +0000 (12:04 +0200)]
stm32mp: syscon: manage clock when present in device tree

Enable the clocks during syscon probe when they are present in device tree.

This patch avoids a freeze when the SYSCFG clock is not enabled by
TF-A / OP-TEE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoclk: stm32mp1: add support of SYSCFG clock
Patrick Delaunay [Tue, 29 Jun 2021 10:04:22 +0000 (12:04 +0200)]
clk: stm32mp1: add support of SYSCFG clock

Add the support of SYSCFG clock used by syscon driver
to prepare the clock management of STM32MP_SYSCON_SYSCFG.

This clock is already defined in kernel device tree,
stm32mp151.dtsi but not yet supported in the syscon driver:

syscfg: syscon@50020000 {
compatible = "st,stm32mp157-syscfg", "syscon";
reg = <0x50020000 0x400>;
clocks = <&rcc SYSCFG>;
};

It is safe to support this clock in U-Boot driver with
RCC_MC_APB3ENSETR, Bit 11 SYSCFGEN: SYSCFG peripheral clocks
enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agoarm: dts: stm32mp15: alignment with v5.13
Patrick Delaunay [Tue, 29 Jun 2021 10:01:07 +0000 (12:01 +0200)]
arm: dts: stm32mp15: alignment with v5.13

Device tree alignment with Linux kernel v5.13
- ARM: dts: stm32: Add PTP clock to Ethernet controller
- ARM: dts: stm32: enable the analog filter for all I2C nodes in
  stm32mp151
- ARM: dts: stm32: fix usart 2 & 3 pinconf to wake up with flow control
- ARM: dts: stm32: Add wakeup management on stm32mp15x UART nodes
- ARM: dts: stm32: add #clock-cells property to usbphyc node on stm32mp151
- ARM: dts: stm32: Add STM32MP1 I2C6 SDA/SCL pinmux
- ARM: dts: stm32: Rename mmc controller nodes to mmc@
- ARM: dts: stm32: Add additional init state for SDMMC1 pins

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: add subcommand close
Patrick Delaunay [Mon, 28 Jun 2021 12:56:03 +0000 (14:56 +0200)]
stm32mp: cmd_stm32key: add subcommand close

The expected sequence to close the device

1/ Load key in DDR with any supported load command
2/ Update OTP with key: STM32MP> stm32key read <addr>

At this point the device is able to perform image authentication but
non-authenticated images can still be used and executed.
So it is the last moment to test boot with signed binary and
check that the ROM code accepts them.

3/ Close the device: only signed binary will be accepted !!
   STM32MP> stm32key close

Warning: Programming these OTP is an irreversible operation!
         This may brick your system if the HASH of key is invalid

This command should be deactivated by default in real product.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: add read OTP subcommand
Patrick Delaunay [Mon, 28 Jun 2021 12:56:02 +0000 (14:56 +0200)]
stm32mp: cmd_stm32key: add read OTP subcommand

Allow to read the OTP value and lock status with the command
$> stm32key read.

This patch also protects the stm32key fuse command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: add get_misc_dev function
Patrick Delaunay [Mon, 28 Jun 2021 12:56:01 +0000 (14:56 +0200)]
stm32mp: cmd_stm32key: add get_misc_dev function

Add a helper function to access to BSEC misc driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: lock of PKH OTP after fuse
Patrick Delaunay [Mon, 28 Jun 2021 12:56:00 +0000 (14:56 +0200)]
stm32mp: cmd_stm32key: lock of PKH OTP after fuse

Lock the OTP value of key's hash after the command
$> stm32key fuse <address>

This operation forbids a second update of these OTP as they are
ECC protected in BSEC: any update of these OTP with a different value
causes a BSEC disturb error and the closed chip will be bricked.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: handle error in fuse_hash_value
Patrick Delaunay [Mon, 28 Jun 2021 12:55:59 +0000 (14:55 +0200)]
stm32mp: cmd_stm32key: handle error in fuse_hash_value

Handle errors in fuse_hash_value function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: cmd_stm32key: use sub command
Patrick Delaunay [Mon, 28 Jun 2021 12:55:58 +0000 (14:55 +0200)]
stm32mp: cmd_stm32key: use sub command

Simplify parsing the command argument by using
the macro U_BOOT_CMD_WITH_SUBCMDS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: configs: activate the command stm32key only for ST boards
Patrick Delaunay [Mon, 28 Jun 2021 12:55:57 +0000 (14:55 +0200)]
stm32mp: configs: activate the command stm32key only for ST boards

This command is used to evaluate the secure boot on stm32mp SOC,
it is deactivated by default in real products.

We activate this command only in STMicroelectronics defconfig
used with the evaluation boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agostm32mp: stm32prog: fix the content of short help message
Patrick Delaunay [Mon, 28 Jun 2021 12:44:33 +0000 (14:44 +0200)]
stm32mp: stm32prog: fix the content of short help message

Reduce the content of short help message for stm32prog command and
removed the carriage return to fix the display of 'help' command when
this command is activated.

Fixes: 954bd1a923a6 ("stm32mp: add the command stm32prog")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
3 years agoconfigs: stm32mp1: remove splashimage and add fdtoverlay_addr_r
Patrick Delaunay [Mon, 28 Jun 2021 12:42:08 +0000 (14:42 +0200)]
configs: stm32mp1: remove splashimage and add fdtoverlay_addr_r

Add the variable used by PXE command for fdtoverlays support
since the commit 69076dff2284 ("cmd: pxe: add support for FDT overlays").

Reused the unused "splashimage" address as CONFIG_SPLASH_SOURCE and
CONFIG_VIDEO_LOGO are not activated and U-Boot display the "BACKGROUND"
image found in extlinux.conf to manage splashscreen on stm32mp1 boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
3 years agortc: m41t62: fix wrong register use for set/reset ST bit
Max Yang [Mon, 10 May 2021 05:23:37 +0000 (05:23 +0000)]
rtc: m41t62: fix wrong register use for set/reset ST bit

Fix wrong register use when set/reset ST bit.
ST bit is in register M41T62_REG_SEC not in M41T62_REG_ALARM_HOUR.

I have not actually tested this. But this seemed buggy from inspection.

Fixes: 9bbe210512c4539 ("rtc: m41t62: add oscillator fail bit reset support")
Signed-off-by: Max Yang <max.yang@deltaww.com>
3 years agoimage: android: Automatically detect more compression types
Stephan Gerhold [Thu, 1 Jul 2021 18:33:16 +0000 (20:33 +0200)]
image: android: Automatically detect more compression types

At the moment android_image_get_kcomp() can automatically detect
LZ4 compressed kernels and the compression specified in uImages.
However, especially on ARM64 Linux is often compressed with GZIP.
Attempting to boot an Android image with a GZIP compressed kernel
image currently results in a very strange crash, e.g.

  Starting kernel ...
  "Synchronous Abort" handler, esr 0x02000000
   ...
  Code: 5555d555 55555d55 555f5555 5d555d55 (00088b1f)

Note the 1f8b, which are the "magic" bytes for GZIP images.

U-Boot already has the image_decomp_type() function that checks for
the magic bytes of bzip2, gzip, lzma and lzo. It's easy to make use
of it here to increase the chance that we do the right thing and the
user does not become confused with strange crashes.

This allows booting Android boot images that contain GZIP-compressed
kernel images.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
3 years agofit: Load DTO into temporary buffer and ignore load address
Marek Vasut [Fri, 11 Jun 2021 02:09:56 +0000 (04:09 +0200)]
fit: Load DTO into temporary buffer and ignore load address

The current fitImage DTO implementation expects each fitImage image
subnode containing DTO to have 'load' property, pointing somewhere
into memory where the DTO will be loaded. The address in the 'load'
property must be different then the base DT load address and there
must be sufficient amount of space between those two addresses.
Selecting and using such hard-coded addresses is fragile, error
prone and difficult to port even across devices with the same SoC
and different DRAM sizes.

The DTO cannot be applied in-place because fdt_overlay_apply_verbose()
modifies the DTO when applying it onto the base DT, so if the DTO was
used in place within the fitImage, call to fdt_overlay_apply_verbose()
would corrupt the fitImage.

Instead of copying the DTO to a specific hard-coded load address,
allocate a buffer, copy the DTO into that buffer, apply the DTO onto
the base DT, and free the buffer.

The upside of this approach is that it is no longer necessary to
select and hard-code specific DTO load address into the DTO. The
slight downside is the new malloc()/free() overhead for each DTO,
but that is negligible (*).

(*) on iMX8MM/MN and STM32MP1

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Add <linux/sizes.h>]
Signed-off-by: Tom Rini <trini@konsulko.com>
3 years agolib/vsprintf.c: remove unused ip6_addr_string()
Rasmus Villemoes [Thu, 27 May 2021 22:20:46 +0000 (00:20 +0200)]
lib/vsprintf.c: remove unused ip6_addr_string()

There's currently no user of %p[iI]6, so including ip6_addr_string()
in the image is a waste of bytes. It's easy enough to have the
compiler elide it without removing the code completely.

The closest I can find to anybody "handling" ipv6 in U-Boot currently
is in efi_net.c which does

        if (ipv6) {
                ret = EFI_UNSUPPORTED;

As indicated in the comment, it can easily be put back, but preferably
under a config knob.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
3 years agolib/vsprintf.c: remove stale comment
Rasmus Villemoes [Thu, 27 May 2021 22:20:45 +0000 (00:20 +0200)]
lib/vsprintf.c: remove stale comment

U-Boot doesn't support %pS/%pF or any other kind of kallsyms-like
lookups. Remove the comment.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
3 years agolib/vsprintf.c: implement printf() in terms of vprintf()
Rasmus Villemoes [Thu, 27 May 2021 22:20:44 +0000 (00:20 +0200)]
lib/vsprintf.c: implement printf() in terms of vprintf()

This saves some code, both in terms of #LOC and .text size, and it is
also the normal convention that foo(...) is implemented in terms of
vfoo().

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
3 years agoclk: Detect failure to set defaults
Simon Glass [Fri, 14 May 2021 01:39:31 +0000 (19:39 -0600)]
clk: Detect failure to set defaults

When the default clocks cannot be set, the clock is silently probed and
the error is ignored. This is incorrect, since having the clocks at the
correct speed may be important for operation of the system.

Fix it by checking the return code.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agosandbox: Silence coverity warning in state_read_file()
Simon Glass [Fri, 14 May 2021 01:39:30 +0000 (19:39 -0600)]
sandbox: Silence coverity warning in state_read_file()

In this case the value seems save to pass to os_free(). Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 165109)
3 years agotpm: Check outgoing command size
Simon Glass [Fri, 14 May 2021 01:39:29 +0000 (19:39 -0600)]
tpm: Check outgoing command size

In tpm_sendrecv_command() the command buffer is passed in. If a mistake is
somehow made in setting this up, the size could be out of range. Add a
sanity check for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331152)
3 years agopinctrl: Avoid coverity warning when checking width
Simon Glass [Fri, 14 May 2021 01:39:28 +0000 (19:39 -0600)]
pinctrl: Avoid coverity warning when checking width

The width is set up in single_of_to_plat() and can only have three values,
all of which result in a non-zero divisor. Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331154)
3 years agocbfs: Check offset range when reading a file
Simon Glass [Fri, 14 May 2021 01:39:27 +0000 (19:39 -0600)]
cbfs: Check offset range when reading a file

Add a check that the offset is within the allowed range.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331155)
3 years agosandbox: cros_ec: Update error handling when reading matrix
Simon Glass [Fri, 14 May 2021 01:39:26 +0000 (19:39 -0600)]
sandbox: cros_ec: Update error handling when reading matrix

At present the return value of ofnode_get_property() is not checked, which
causes a coverity warning. While we are here, use logging for the errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 331157)
3 years agodm: core: Check uclass_get() return value when dumping
Simon Glass [Fri, 14 May 2021 01:39:24 +0000 (19:39 -0600)]
dm: core: Check uclass_get() return value when dumping

Update dm_dump_drivers() to use the return value from uclass_get() to
check the validity of uc. This is equivalent and should be more attractive
to Coverity.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 316601)
3 years agoreset: Avoid a warning in devm_regmap_init()
Simon Glass [Fri, 14 May 2021 01:39:22 +0000 (19:39 -0600)]
reset: Avoid a warning in devm_regmap_init()

The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.

Nevertheless this is intended. Add a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 312951)
3 years agoreset: Avoid a warning in devm_reset_bulk_get_by_node()
Simon Glass [Fri, 14 May 2021 01:39:21 +0000 (19:39 -0600)]
reset: Avoid a warning in devm_reset_bulk_get_by_node()

The devres_alloc() function is intended to avoid the need for freeing
memory, although in practice it may not be enabled, thus leading to a true
leak.

Nevertheless this is intended. Add a comment to explain this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 312952)
3 years agotools: Avoid showing return value of clock_gettime()
Simon Glass [Fri, 14 May 2021 01:39:20 +0000 (19:39 -0600)]
tools: Avoid showing return value of clock_gettime()

This value is either 0 for success or -1 for error. Coverity reports that
"ret" is passed to a parameter that cannot be negative, pointing to the
condition 'if (ret < 0)'.

Adjust it to just check for non-zero and avoid showing -1 in the error
message, which is pointless. Perhaps these changes will molify Coverity.

Reported-by: Coverity (CID: 312956)
Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agotest: Rename final check in setexpr_test_backref()
Simon Glass [Fri, 14 May 2021 01:39:19 +0000 (19:39 -0600)]
test: Rename final check in setexpr_test_backref()

The bug in setexpr is fixed now, so this test can be enabled.

Reported-by: Coverity (CID: 316346)
Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agovideo: Check return value in pwm_backlight_of_to_plat()
Simon Glass [Fri, 14 May 2021 01:39:18 +0000 (19:39 -0600)]
video: Check return value in pwm_backlight_of_to_plat()

This cannot actually fail, but check the value anyway to keep coverity
happy.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 316351)
3 years agosandbox: net: Ensure host name is always a valid string
Simon Glass [Fri, 14 May 2021 01:39:17 +0000 (19:39 -0600)]
sandbox: net: Ensure host name is always a valid string

At present if ifname is exactly IFNAMSIZ characters then it will result
in an unterminated string. Fix this by using strlcpy() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 316358)
Acked-by: Ramon Fried <rfried.dev@gmail.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-x86
Tom Rini [Thu, 15 Jul 2021 15:06:24 +0000 (11:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-x86

- x86: various improvements made in getting Chromium OS verified boot
  running on top of coreboot, booting into U-Boot.

3 years agox86: Ensure the e820 map is installed in all cases
Simon Glass [Sun, 11 Jul 2021 03:15:21 +0000 (21:15 -0600)]
x86: Ensure the e820 map is installed in all cases

This is a revert of a recent logic change in setup_zimage(). We do
actually need to install this information always. Change it to install
from the Coreboot tables if available, else the normal source.

Fixes: e7bae8283fe ("x86: Allow installing an e820 when booting from coreboot")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agodoc: Update documentation for cros-2021.04 release
Simon Glass [Sun, 27 Jun 2021 23:51:11 +0000 (17:51 -0600)]
doc: Update documentation for cros-2021.04 release

With the new 2021.04 we have a new version of Chromium OS boot, which
supports sandbox, coral and coral-on-coreboot. Add documentation for
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agodtoc: Check that a parent is not missing
Simon Glass [Sun, 27 Jun 2021 23:51:10 +0000 (17:51 -0600)]
dtoc: Check that a parent is not missing

With of-platdata-inst we want to set up a reference to each devices'
parent device, if there is one. If we find that the device has a parent
(i.e. is not a root node) but it is not in the list of devices being
written, then we cannot create the reference.

Report an error in this case, since it indicates that the parent node
is either missing a compatible string, is disabled, or perhaps does not
have any properties because it was not tagged for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
3 years agox86: cros: Check ROM exists before building vboot
Simon Glass [Sun, 27 Jun 2021 23:51:09 +0000 (17:51 -0600)]
x86: cros: Check ROM exists before building vboot

All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agox86: coreboot: Document the memory map
Simon Glass [Sun, 27 Jun 2021 23:51:08 +0000 (17:51 -0600)]
x86: coreboot: Document the memory map

Add information about memory usage when U-Boot is started from coreboot.
This is useful when debugging. Also, since coreboot takes a chunk of
memory in the middle of SDRAM for use by PCI devices, it can help avoid
overwriting this with a loaded kernel by accident.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: coreboot: Use vendor in the Kconfig
Simon Glass [Sun, 27 Jun 2021 23:51:07 +0000 (17:51 -0600)]
x86: coreboot: Use vendor in the Kconfig

Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Add function comments to cb_sysinfo.h
Simon Glass [Sun, 27 Jun 2021 23:51:06 +0000 (17:51 -0600)]
x86: Add function comments to cb_sysinfo.h

Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: coral: Allow booting from coreboot
Simon Glass [Sun, 27 Jun 2021 23:51:05 +0000 (17:51 -0600)]
x86: coral: Allow booting from coreboot

Set up coral so that it can boot from coreboot, even though it is a
bare-metal build. This helps with testing since the same image can be used
in both cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: coreboot: Show the BIOS date
Simon Glass [Sun, 27 Jun 2021 23:51:04 +0000 (17:51 -0600)]
x86: coreboot: Show the BIOS date

The BIOS version may not be present, e.g. on a Chrome OS build. Add the
BIOS date as well, so we get some sort of indication of coreboot's
vintage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Do cache set-up by default when booting from coreboot
Simon Glass [Sun, 27 Jun 2021 23:51:03 +0000 (17:51 -0600)]
x86: Do cache set-up by default when booting from coreboot

A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.

If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Update the MP constants to avoid conflicts
Simon Glass [Sun, 27 Jun 2021 23:51:02 +0000 (17:51 -0600)]
x86: Update the MP constants to avoid conflicts

These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.

Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.

This fixes the 'mtrr' command when CONFIG_SMP is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agox86: Don't set up MTRRs if previously done
Simon Glass [Sun, 27 Jun 2021 23:51:01 +0000 (17:51 -0600)]
x86: Don't set up MTRRs if previously done

When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.

Skip that step in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agotpm: cr50: Drop unnecessary coral headers
Simon Glass [Sun, 27 Jun 2021 23:51:00 +0000 (17:51 -0600)]
tpm: cr50: Drop unnecessary coral headers

These headers are not actually used. Drop them so that this driver can
be used by other boards, e.g. coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agospi: ich: Don't require the PCH
Simon Glass [Sun, 27 Jun 2021 23:50:59 +0000 (17:50 -0600)]
spi: ich: Don't require the PCH

When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
3 years agox86: pci: Allow binding of some devices before relocation
Simon Glass [Sun, 27 Jun 2021 23:50:57 +0000 (17:50 -0600)]
x86: pci: Allow binding of some devices before relocation

At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.

Use the PCI_VENDEV() macro to encode the cell value. This is present in
U-Boot but not used, so move it to the binding header-file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agopci: Use const for pci_find_device_id() etc.
Simon Glass [Sun, 27 Jun 2021 23:50:56 +0000 (17:50 -0600)]
pci: Use const for pci_find_device_id() etc.

These functions don't modify the device-ID struct that is passed in, so
mark the argument as const, so the data structure can be declared that
way. This allows it to be placed in the rodata section.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
3 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Thu, 15 Jul 2021 11:11:06 +0000 (07:11 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Turris_omnia/mox: SPI NOR and MTD related changes / fixes (Marek)
- a37xx: pci: Misc fixes / optimizations (Pali)
- Espressobin: Fix setting $fdtfile env & changes in MMC detection
  (Pali)
- MMC: mmc_get_op_cond: Allow quiet detection of eMMC (Pali)

3 years agommc: mmc_get_op_cond: Allow quiet detection of eMMC
Pali Rohár [Wed, 14 Jul 2021 14:37:29 +0000 (16:37 +0200)]
mmc: mmc_get_op_cond: Allow quiet detection of eMMC

Add a new 'quiet' argument to mmc_get_op_cond() function which avoids
printing error message when SD/eMMC card is not detected.

Espressobin and mx6cuboxi boards use this function for detecting presence
of eMMC and therefore it is expected and normal that eMMC does not have to
be connected. So error message "Card did not respond to voltage select!"
should be skipped in this case as it is not an error.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
3 years agoarm: mvebu: Espressobin: Use function mmc_get_op_cond() for detecting eMMC
Pali Rohár [Wed, 14 Jul 2021 14:37:28 +0000 (16:37 +0200)]
arm: mvebu: Espressobin: Use function mmc_get_op_cond() for detecting eMMC

Use function mmc_get_op_cond() instead of mmc_init() for detecting presence
of eMMC. Documentation for this function says that it could be used to
detect the presence of SD/eMMC when no card detect logic is available.

This function is also used by mx6cuboxi board for detecting presence of eMMC.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: Espressobin: Fix setting $fdtfile env
Pali Rohár [Wed, 14 Jul 2021 14:37:27 +0000 (16:37 +0200)]
arm: mvebu: Espressobin: Fix setting $fdtfile env

Ensure that 'env default -a' always set correct value to $fdtfile, even
when custom user variable is already stored in non-volatile env storage
(means that env_get("fdtfile") call returns non-NULL value).

As default value is now correctly set like if specified at compile time in
CONFIG_EXTRA_ENV_SETTINGS, there is no need to set $fdtfile explicitly via
env_set("fdtfile", ...) call.

So remove wrong skip based on env_get("fdtfile") and then also unneeded
env_set("fdtfile", ...) call.

Fixes: c4df0f6f315c ("arm: mvebu: Espressobin: Set default value for $fdtfile env variable")
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: armada-3720: remove unused config option
Marek Behún [Fri, 9 Jul 2021 15:40:59 +0000 (17:40 +0200)]
arm: mvebu: armada-3720: remove unused config option

The config option CONFIG_DEBUG_UART_CLOCK is not used by Armada 3720's
serial driver (it wasn't even before the recent update of that driver).

Even if it was used, the value was incorrect (the frequency of the clock
is 25 MHz, not 25.8048 MHz).

Remove it from config files and set the default value to 0.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_{omnia, mox}: enable MTD command
Marek Behún [Fri, 9 Jul 2021 14:56:14 +0000 (16:56 +0200)]
arm: mvebu: turris_{omnia, mox}: enable MTD command

Now that the MTD subsystem properly supports OF partitions of a SPI NOR,
we can enable the MTD command and start using it instead of the
deprecated sf command.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: mvebu: turris_omnia: force 40 MHz speed on SPI NOR
Marek Behún [Fri, 9 Jul 2021 14:56:13 +0000 (16:56 +0200)]
arm: mvebu: turris_omnia: force 40 MHz speed on SPI NOR

Commit e2e95e5e2542 ("spi: Update speed/mode on change") changed the
boot time on Turris Omnia from ~2.3s to over 8s, due to SPL loading main
U-Boot from SPI NOR at 1 MHz instead of 40 MHz.

This is because the SPL code passes the CONFIG_SF_DEFAULT_SPEED option
to spi_flash_probe(), and with the above commit spi_flash_probe() starts
prefering this parameter instead of the one specified in device-tree.

The proper solution here would probably be to fix the SF subsystem to
prefer the frequency specified in the device-tree, if it is present, but
I am not sure what else will be affected on other boards with such a
change. So until then we need a more simple fix.

Since the CONFIG_SF_DEFAULT_SPEED option is used by the code, put the
correct value there for Turris Omnia. Also put the correct value to
CONFIG_SF_DEFAULT_MODE and use 40 MHz when reading environment.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
3 years agoarm: a37xx: pci: Fix typo in comment
Pali Rohár [Thu, 8 Jul 2021 18:19:00 +0000 (20:19 +0200)]
arm: a37xx: pci: Fix typo in comment

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>