Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.
For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
UBI: fixable bit-flip detected at PEB 1027
UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
UBI: fixable bit-flip detected at PEB 4083
UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
UBI DBG: erase_worker: erase PEB 4083 EC 55
UBI DBG: sync_erase: erase PEB 4083, old EC 55
UBI DBG: do_sync_erase: erase PEB 4083
UBI DBG: sync_erase: erased PEB 4083, new EC 56
UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
UBI DBG: ensure_wear_leveling: schedule scrubbing
UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
...
This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Sat, 5 Oct 2013 19:07:25 +0000 (21:07 +0200)]
Fix number base handling of "load" command
As documented, almost all U-Boot commands expect numbers to be entered
in hexadecimal input format. (Exception: for historical reasons, the
"sleep" command takes its argument in decimal input format.)
This rule was broken for the "load" command; for details please see
especially commits 045fa1e "fs: add filesystem switch libary,
implement ls and fsload commands" and 3f83c87 "fs: fix number base
behaviour change in fatload/ext*load". In the result, the load
command would always require an explicit "0x" prefix for regular
(i. e. base 16 formatted) input.
Change this to use the standard notation of base 16 input format.
While strictly speaking this is a change of the user interface, we
hope that it will not cause trouble. Stephen Warren comments (see
[1]):
I suppose you can change the behaviour if you want; anyone
writing "0x..." for their values presumably won't be
affected, and if people really do assume all values in U-Boot
are in hex, presumably nobody currently relies upon using
non-prefixed values with the generic load command, since it
doesn't work like that right now.
pci: Properly configure prefetchable memory region
Forcibly set hose->pci_prefetch to NULL to make sure it will be setup.
This will help if for any reason callers didn't make sure themselves to
NULL the field.
Andre Przywara [Mon, 7 Oct 2013 08:56:51 +0000 (10:56 +0200)]
ARM: virtualization: replace verbose license with SPDX identifier
The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Otavio Salvador [Thu, 3 Oct 2013 11:04:38 +0000 (08:04 -0300)]
mtd: Fix function description in part_validate comment
The part_validate comment had a wrong description of the actions it
does and referenced to non-existent functions while in fact it calls
'part_validate_eraseblock()'.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Andre Przywara [Thu, 19 Sep 2013 16:06:46 +0000 (18:06 +0200)]
ARM: VExpress: enable ARMv7 virt support for VExpress A15
To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.
This also serves as an example for what to do when adding support for
new boards.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:45 +0000 (18:06 +0200)]
ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.
While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).
The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.
In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.
The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:44 +0000 (18:06 +0200)]
ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.
The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:43 +0000 (18:06 +0200)]
ARM: trigger non-secure state switch during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:42 +0000 (18:06 +0200)]
ARM: add C function to switch to non-secure state
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0xFFFFFFFF)
The core specific GIC setup is then done in the assembly routine.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:41 +0000 (18:06 +0200)]
ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.
Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
(GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
(GICC_PMR = 0xFF)
Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.
The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.
After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.
Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Andre Przywara [Thu, 19 Sep 2013 16:06:40 +0000 (18:06 +0200)]
ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Simon Glass [Mon, 23 Sep 2013 23:35:17 +0000 (17:35 -0600)]
buildman: Allow make flags to be specified for each board
There are a few make options such as BUILD_TAG which can be provided when
building U-Boot. Provide a way for buildman to pass these flags to make
also.
The flags should be in a [make-flags] section and arranged by target name
(the 'target' column in boards.cfg. See the README for more details.
Julius Werner [Tue, 24 Sep 2013 17:53:07 +0000 (10:53 -0700)]
usb: ehci: Fix test mode for connected ports
The EHCI controller has some very specific requirements for the USB 2.0
port test modes, which were not closely followed in the initial test
mode commit. It demands that the host controller is completely shut down
(all ports suspended, Run/Stop bit unset) when activating test mode, and
will not work on an already enumerated port.
This patch fixes that by introducing a new ehci_shutdown() function that
closely follows the procedure listed in EHCI 4.14. Also, when we have
such a function anyway, we might as well also use it in
usb_lowlevel_stop() to make the normal host controller shutdown cleaner.
Signed-off-by: Julius Werner <jwerner@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
usb:g_dnl:dfu: Download gadget and DFU function code clean up
The download gadget code and DFU function lacks of proper declarations
for the case when a target board wants to use only one of available usb
functions.
Moreover the relevant declarations have been moved to consistent
localization (like <dfu.h>).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
usb:g_dnl:ums: Conditional compilation for mass storage function (f_mass_storage)
The mass storage composite function is now compiled in only when
CONFIG_USB_GADGET_MASS_STORAGE is defined.
Such change provides binary size reduction for boards which use USB
download gadget (like am335x_evm) with DFU, but don't use UMS.
For example at am335x_evm board reduction is more than 2KiB for
text and around 120B for data.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
Afzal Mohammed [Tue, 17 Sep 2013 19:45:24 +0000 (01:15 +0530)]
dfu: ram support
DFU spec mentions it as a method to upgrade firmware (software stored
in writable non-volatile memory). It also says other potential uses of
DFU is beyond scope of the spec.
Here such a beyond the scope use is being attempted - directly pumping
binary images from host via USB to RAM. This facility is a developer
centric one in that it gives advantage over upgrading non-volatile
memory for testing new images every time during development and/or
testing.
Directly putting image onto RAM would speed up upgrade process. This and
convenience was the initial thoughts that led to doing this, speed
improvement over MMC was only 1 second though - 6 sec on RAM as opposed
to 7 sec on MMC in beagle bone, perhaps enabling cache and/or optimizing
DFU framework to avoid multiple copy for ram (if worth) may help, and
on other platforms and other boot media like NAND maybe improvement
would be higher.
And for a platform that doesn't yet have proper DFU suppport for
non-volatile media's, DFU to RAM can be used.
Another minor advantage would be to increase life of mmc/nand as it
would be less used during development/testing.
Downloading images to RAM using DFU is not something new, this is
acheived in openmoko also.
DFU on RAM can be used for extracting RAM contents to host using dfu
upload. Perhaps this can be extended to io for squeezing out register
dump through usb, if it is worth.
Signed-off-by: Afzal Mohammed <afzal.mohd.ma@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Gerhard Sittig <gsi@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Heiko Schocher <hs@denx.de>
Afzal Mohammed [Tue, 17 Sep 2013 19:44:50 +0000 (01:14 +0530)]
dfu: unify mmc/nand read/write ops enum
MMC and NAND independently defines same enumerators for read/write.
Unify them by defining enum in dfu header. RAM support that is being
added newly also can make use of it.
As seen with codesourcery compiler 2010q1, the buf pointer in
usb_request structure is not aligned on 4 bytes boundary causing
data aborts in eth_setup -> conf_buf -> usb_gadget_config_buf.
Make it as align access to fix this issue.
dfu: Make maximum DFU file size equal to default DFU data buffer
Up till now the DFU maximum file size (to be written to e.g. eMMC)
was different from the DFU data buffer size. It caused errors when
one buffer was smaller than data to be written.
Now, the maximum DFU file size is equal to default DFU buffer size.
In spite of this, user is still able to manually adjust those default
values.
Joel Fernandes [Wed, 4 Sep 2013 23:55:14 +0000 (18:55 -0500)]
usb: gadget: Fix data aborts during USB ethernet boot
As seen on GCC 4.6 Linaro compiler, control_req buffer is not aligned
on 4 byte boundaray causing data aborts in eth_setup -> conf_buf
during dhcp boot over usb_ether. Fix the issue my aligning control_req
buffer using DEFINE_CACHE_ALIGN_BUFFER.
Tested on am335x_evm platform (beaglebone).
Applies on 2013.10-rc1 branch.
Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Joel Fernandes <joelf@ti.com>
This patch makes the necessary changes for making use of
I2S0 channel instead of I2S1 channel on smdk board. This
changes are done to maintain the uniformity to use I2S0 channel.
Tom Rini [Tue, 24 Sep 2013 13:05:08 +0000 (09:05 -0400)]
cmd_pxe.c: Pass along 'cmdtp' to do_bootm()/do_bootz()
When we call do_bootm() with a vmlinuz, this would lead to a NULL
pointer dereference, and after talking with Wolfgang the right thing to
do here for now is to make sure that we pass cmdtp to these functions
rather than NULL.
Reported-by: Steven A. Falco <stevenfalco@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Mon, 23 Sep 2013 18:20:37 +0000 (14:20 -0400)]
cmd_bootm.c: Only pass BOOTM_STATE_OS_CMDLINE on PowerPC/MIPS
In 5c427e4 we pass BOOTM_STATE_OS_CMDLINE as part of the bootm states to
run, on all arches. However, this is only valid / useful on PowerPC and
MIPS, and causes a problem on ARM where we specifically do not use it.
Rather than make this state fake pass like we do for GO on some arches
(which need updating to use the GO state), we should just not pass
CMDLINE except when it may be used, like before.
Tested-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
r9 is a platform-specific register in ARM EABI and not per
definition a general purpose register. Do not use it while
relocating so it can be used for gd.
cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Michal Simek [Wed, 28 Aug 2013 05:36:31 +0000 (07:36 +0200)]
arm: zynq: Fix timer loadaddress
Reload address was written to the counter register
instead of load register.
The problem happens when timer expires but never
reload to ~0UL (it is downcount timer).
Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeroen Hofstee [Sat, 24 Aug 2013 11:55:38 +0000 (13:55 +0200)]
arm: prevent using movt/movw address loads
The movt/movw instruction can be used to hardcode an
memory location in the instruction itself. The linker
starts complaining about this if the compiler decides
to do so: "relocation R_ARM_MOVW_ABS_NC against `a local
symbol' can not be used" and it is not support by U-boot
as well. Prevent their use by requiring word relocations.
This allows u-boot to be build at other optimalization
levels then -Os.
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: TigerLiu@viatech.com.cn Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Simon Glass <sjg@chromium.org>
am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot.
If, in CONFIG_BOOTCOMMAND, the environment switches both the mmcdev
and bootpart variables to refer to MMC device 1, it would make sense
that the mmcroot env variable should switch to that device as well.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
if phy_connect() did not find a phy, phydev is NULL and
following code in cpsw_phy_init() crashes. Fix this.
Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Lokesh Vutla [Fri, 23 Aug 2013 12:04:17 +0000 (17:34 +0530)]
ARM: OMAP5: Avoid writing into LDO SRAM bits
Writing magic bits into LDO SRAM was suggested only for OMAP5432
ES1.0. Now these are no longer applicable. Moreover these bits should
not be overwritten as they are loaded from EFUSE. So avoid
writing into these registers.
Steve Kipisz [Wed, 14 Aug 2013 14:51:31 +0000 (10:51 -0400)]
am335x:Handle worst case scenario for Errata 1.0.24
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
[trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
Tom Rini [Fri, 30 Aug 2013 20:28:46 +0000 (16:28 -0400)]
am335x_evm: am33xx_spl_board_init function and scale core frequency
Add a am33xx_spl_board_init (and enable the PMICs) that we may see,
depending on the board we are running on. In all cases, we see if we
can rely on the efuse_sma register to tell us the maximum speed. In the
case of Beaglebone White, we need to make sure we are on AC power, and
are on later than rev A1, and then we can ramp up to the PG1.0 maximum
of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that
supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we
cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we
need to rely on the efuse_sma if we are on PG2.1, and the defaults for
PG1.0/2.0.
Fix wrong sdhci host control register read and write
The patch fixes the improper read and write of sdhci
host control register for sdma transfer.
The problem comes when reading and writing 1 byte long
host control register with the sdhci_readl() and
sdhci_writel(). The misuse of these functions overwrite
the value of the next registers which are in 4 bytes boundary.
This patch replaces four byte register read/write functions
with one byte read/write ones. Beside, it eliminates
unnecessary bit operation. i.e. or-ing zero against a variable.
Without those it's very easy to make mistakes when for instance
the 'size' field is more than just a constant.
Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Marek Vasut <marex@denx.de> Cc: Anton Staaf <robotboy@chromium.org> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de>
mmc/dw_mmc: Allocate the correct amount of descriptors
This fixes two issues:
* a descriptor was allocated for every block, while a descriptor can
take 8 blocks
* there was an off-by-one error in the descriptor preparation: there
were two last descriptors, one with length==0
In dwmci_prepare_data, the descriptors are allocated for DMA transfer.
These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses
the stack to allocate these descriptors. This becomes a problem if the
DMA transfer continues after the processor leaves the function in which
the descriptors were allocated.
Therefore, I have moved the allocated of the buffers up one level, to
dwmci_send_cmd(). The DMA transfer should be complete when leaving this
function.
Paul Burton [Mon, 9 Sep 2013 14:30:26 +0000 (15:30 +0100)]
mmc: don't support write & erase for SPL builds
For SPL builds this is just dead code since we'll only need to read.
Eliminating it results in a significant size reduction for the SPL
binary, which may be critical for certain platforms where the binary
size is highly constrained.
Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
doc: README.mxs: Add instruction to install 'libssl-dev'
Since commit bce883707 (ARM: mxs: tools: Add mkimage support for MXS bootstream)
the following build error is seen when doing a MAKEALL build:
$ ./MAKEALL mx28evk
Configuring for mx28evk - Board: mx28evk, Options: ENV_IS_IN_MMC
mxsimage.c:18:25: fatal error: openssl/evp.h: No such file or directory
Add an entry about the need of installing the 'libssl-dev' package.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
mx6sabresd: Avoid hang when HDMI cable is not connected
Since commit d9b894603 (mx6sabresd: Add LVDS splash screen support) the
following hang happens if the HDMI cable is not connected or the 'panel'
variable is not set:
wandboard: Use imx6dl-wandboard.dtb for the solo version
The wandboard solo version should boot the 'imx6dl-wandboard.dtb' file, since
dual-lite and solo variants are the same SoC with only the number of cores being
different.
Tom Rini [Fri, 30 Aug 2013 20:28:45 +0000 (16:28 -0400)]
am33xx: Add the efuse_sma CONTROL_MODULE register
Starting with PG2.1 we have a register in the CONTROL_MODULE that is set
with the package type and maximum supported frequency. Add this, and
the relevant mask/values.
Tom Rini [Fri, 30 Aug 2013 20:28:44 +0000 (16:28 -0400)]
am33xx: Add am33xx_spl_board_init function, call
We need to allow for a further call-out in spl_board_init. Call this
am33xx_spl_board_init and add a __weak version. This function may be
used to scale the MPU frequency up, depending on board needs.
Philip, Avinash [Fri, 30 Aug 2013 20:28:43 +0000 (16:28 -0400)]
drivers/power/pmic: Add tps65910 driver
Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM,
AM335x EVM SK and others.
Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
[trini: Split and rework Avinash's changes into new drivers/power
framework] Signed-off-by: Tom Rini <trini@ti.com>
Greg Guyotte [Fri, 30 Aug 2013 20:28:42 +0000 (16:28 -0400)]
drivers/power/pmic: Add tps65217 driver
Add a driver for the TPS65217 PMIC that is found in the Beaglebone
family of boards.
Signed-off-by: Greg Guyotte <gguyotte@ti.com>
[trini: Split and rework Greg's changes into new drivers/power
framework] Signed-off-by: Tom Rini <trini@ti.com>
Wolfgang Denk [Tue, 17 Sep 2013 09:24:06 +0000 (11:24 +0200)]
SPDX: fix IBM-pibs license identifier
The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license. However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word. I'd prefer
to be consistent to this end".
projects / u-boot.git / log
+Oh;st=author){kind=link}
