Stefan Roese [Thu, 7 Apr 2022 07:11:54 +0000 (09:11 +0200)]
mips: octeon: nic23: Enable ethernet support
This patch enables the Kconfig symbols needed for full ethernet support
on the NIC23. Additionally board specific setup is done, mostly GPIOs
related to SFP / GPIO configuration. With this, ethernet can be used on
this board. Here an example of a tftp load:
=> tftp ffffffff81000000 big
Using ethernet-mac-nexus@11800e2000000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.247
Filename 'big'.
Load address: 0xffffffff81000000
Loading: ################################################## 10 MiB
9.7 MiB/s
done
Bytes transferred = 10485760 (a00000 hex)
This patch enables the Kconfig symbols needed for full ethernet support
on the EBB7304. Also the PHY autonegotiation timeout is increased, as
the default 5 seconds are sometime a bit short. With this, ethernet can
be used on this board. Here an example of a tftp load:
=> tftp ffffffff81000000 big
ethernet-mac-nexus@11800e0000000 Waiting for PHY auto negotiation to complete....... done
Using ethernet-mac-nexus@11800e0000000 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.243
Filename 'big'.
Load address: 0xffffffff81000000
Loading: ################################################## 10 MiB
13.2 MiB/s
done
Bytes transferred = 10485760 (a00000 hex)
Stefan Roese [Thu, 7 Apr 2022 07:11:52 +0000 (09:11 +0200)]
net: Add ethernet support for MIPS Octeon
This patchs adds the ethernet & MDIO driver for the MIPS Octeon II / III
SoC platform. Please note that these drivers are based on the 2013
U-Boot version from Marvell and make use of the platform supported
helper functions for the ethernet functionality, including stuff like
SFP handling.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Stefan Roese [Thu, 7 Apr 2022 07:11:48 +0000 (09:11 +0200)]
mips: octeon: octeon_common.h: Move init SP because of increased image size
This patch moves CONFIG_SYS_INIT_SP_OFFSET to a higher address so that
it does not interfere with larger U-Boot images. This was noticed, while
adding network support to the EBB7304 board.
Stefan Roese [Thu, 7 Apr 2022 07:11:46 +0000 (09:11 +0200)]
mips: octeon: cpu.c: Move bootmem init to arch_early_init_r()
Call octeon_bootmem_init() earlier in the boot process, so that this
bootmemory infrastructure is already initialized when e.g. the
networking support gets probed.
Stefan Roese [Thu, 7 Apr 2022 07:11:45 +0000 (09:11 +0200)]
mips: octeon: Makefile: Enable building of the newly added C files
This patch adds the newly added C files to the Makefile to enable
compilation. This is done in a separate step, to not introduce build
breakage while adding the single files with potentially missing
externals.
Aaron Williams [Thu, 7 Apr 2022 07:11:41 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-pko-internal-ports-range.c
Import cvmx-pko-internal-ports-range.c from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 6 May 2021 07:17:53 +0000 (09:17 +0200)]
mips: octeon: Add cvmx-global-resource.c
Import cvmx-global-resource.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:09 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-xcv-defs.h header file
Import cvmx-xcv-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:08 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-pcsxx-defs.h header file
Import cvmx-pcsxxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:07 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-npei-defs.h header file
Import cvmx-npei-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:06 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-lbk-defs.h header file
Import cvmx-lbk-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:05 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-iob-defs.h header file
Import cvmx-iob-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:04 +0000 (09:11 +0200)]
mips: octeon: Add cvmx-ilk-defs.h header file
Import cvmx-igl-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Aaron Williams [Thu, 7 Apr 2022 07:11:03 +0000 (09:11 +0200)]
mips: octeon: Add misc cvmx-* header files
Import misc cvmx-helper header files from 2013 U-Boot. They will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
To quote the author:
The virtio PCI drivers forgo a number of consistency checks,
particularly around pointer validation and bounds checking. This series
focuses on the modern driver to add those checks.
The start of the series adds and fixes some basic bounds checks. Later
patches ensure PCI addresses fall within the expected regions rather
than any arbitrary address. This is acheived by introducing range
parameters to a few of the dm_pci_* functions that allow the ranges to
be checked.
The series also adds a few new configs to allow parts of virtio and PCI
to be disabled where the features may be unused and the current
implementations don't have the needed consistencty checks.
Andrew Scull [Thu, 21 Apr 2022 16:11:15 +0000 (16:11 +0000)]
virtio: pci: Make use of dm_pci_map_bar()
The virtio PCI capabilities describe regions of memory that should be
mapped. Map those with dm_pci_map_bar() which will ensure they are valid
PCI regions.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:14 +0000 (16:11 +0000)]
virtio: pci: Check virtio configs are mapped
Prepare for calls to `virtio_pci_map_capability()` failing by returning
NULL on error. If this happens, later accesses to the pointers would be
unsafe so cause the probe to fail if such an error occurs.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:12 +0000 (16:11 +0000)]
pci: Update dm_pci_bus_to_virt() parameters
Add mask parameter and reorder length parameter to match the other PCI
address conversion functions. Using PCI_REGION_TYPE as the mask gives
the old behaviour.
It's converted from a macro to an inline function as the length
parameter is now used twice, but should only be calculated once.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:11 +0000 (16:11 +0000)]
pci: Match region flags using a mask
When converting addresses, apply a mask to the region flags during
lookup. This allows the caller to specify which flags are important and
which are not, for example to exclude system memory regions.
The behaviour of the function is changed such that they don't
preferentially search for a non-system memory region. However, system
memory regions are added after other regions in decode_regions() leading
to a similar outcome.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:09 +0000 (16:11 +0000)]
test: pci: Test PCI address conversion functions
Add tests for the functions dm_pci_bus_to_phys() and
dm_pci_phys_to_bus() which convert between PCI bus addresses and
physical addresses based on the ranges declared for the PCI controller.
The ranges of bus#1 are used for the tests, adding a translation to one
of the ranges to cover more cases.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:08 +0000 (16:11 +0000)]
pci: Range check address conversions
When converting between PCI bus and physical addresses, include a length
parameter that can be used to check that the entire range fits within
one of the PCI regions. This prevents an address being returned that
might be only partially valid for the range it is going to be used for.
Where the range check is not wanted, passing a length of 0 will have the
same behaviour as before this change.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:07 +0000 (16:11 +0000)]
pci: Check region ranges are addressable
When parsing the `ranges` DT node, check that both extremes of the
regions are addressable without overflow. This assumption can then be
safely made when processing the regions.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:06 +0000 (16:11 +0000)]
pci: Fix use of flags in dm_pci_map_bar()
The flags parameter of dm_pci_map_bar() is used for PCI region flags
rather than memory mapping flags. Fix the type to match that of the
region flags and stop using the regions flags as memory mapping flags.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:05 +0000 (16:11 +0000)]
virtio: pci: Read entire capability into memory
Read the virtio PCI capability out of the device configuration space to
a struct rather than accessing fields directly from the configuration
space as they are needed. This both makes access to the fields easier
and avoids re-reading fields.
Re-reading fields could result in time-of-check to time-of-use problems,
should the value in the configuration space change. The range check of
the `bar` field and the later call to `dm_pci_read_bar32()` is an
example of where this could happen.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:04 +0000 (16:11 +0000)]
virtio: pci: Check virtio capability is in bounds
Ensure the virtio PCI capabilities are contained within the bounds of
the device's configuration space. The expected size of the capability is
passed when searching for the capability to enforce this check.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:03 +0000 (16:11 +0000)]
virtio: pci: Check virtio common config size
Check that the common config is at least as large as the struct it is
expected to contain. Only then is it safe to cast the pointer and be
safe from out-of-bounds accesses.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:01 +0000 (16:11 +0000)]
virtio: pci: Bounds check device config access
The device config is optional, so check it was present and mapped before
trying to use the pointer. Bounds violations are an error, not just a
warning, so bail if the checks fail.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:11:00 +0000 (16:11 +0000)]
virtio: pci: Fix discovery of device config length
The length of the device config was erroneously being taken from the
notify capability. Correct this by finding the length in the device
capability.
Fixes: 550435edf810 ("virtio: pci: Support non-legacy PCI transport device") Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andrew Scull [Thu, 21 Apr 2022 16:10:59 +0000 (16:10 +0000)]
virtio: pci: Allow exclusion of legacy driver
Add a new config to control whether the driver for legacy virtio PCI
devices is included in the build. VIRTIO_PCI_LEGACY is included by
default when VIRTIO_PCI is selected, but it can also be independently
toggled.
Signed-off-by: Andrew Scull <ascull@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Tue, 3 May 2022 12:30:14 +0000 (08:30 -0400)]
CI: Azure: Rework how we update MSYS2
Based on reading https://www.msys2.org/docs/ci/ and "Other Systems"
rework how we update MSYS2 to the current version. We run it once, to
perform nothing other than being the first run, then we run pacman
twice.
U-Boot provides a verified-boot feature based around FIT, but there is
no standard way of implementing it for a board. At present the various
required pieces must be built up separately, to produce a working
implementation. In particular, there is no built-in support for selecting
A/B boot or recovery mode.
This series introduces VPL, a verified program loader phase for U-Boot.
Its purpose is to run the verified-boot process and decide which SPL
binary should be run. It is critical that this decision happens before
SPL runs, since SPL sets up SDRAM and we need to be able to update the
SDRAM-init code in the field.
Adding VPL into the boot flow provides a standard place to implement
verified boot. This series includes the phase itself, some useful Kconfig
options and a sandbox_vpl build for sandbox. No verfied-boot support is
provided in this series.
Most of the patches in this series are fixes and improvements to docs and
various Kconfig conditions for SPL.
Simon Glass [Sat, 30 Apr 2022 06:56:52 +0000 (00:56 -0600)]
Introduce Verifying Program Loader (VPL)
Add support for VPL, a new phase of U-Boot. This runs after TPL. It is
responsible for selecting which SPL binary to run, based on a
verified-boot process.
Simon Glass [Sat, 30 Apr 2022 06:56:50 +0000 (00:56 -0600)]
Makefile: Simplify devicetree rules for SPL/TPL
The current logic checks several options to decide whether SPL/TPL need
the U-Boot devicetree to be built. In fact we can check OF_CONTROL, which
is enabled in all cases that matter.
Chris Packham [Mon, 2 May 2022 03:16:25 +0000 (15:16 +1200)]
ARM: mvebu: x530: set MPP55 to gpio
MPP55 is used as a reset connected to the L3 switch chip. This doesn't
matter for u-boot as it doesn't use the L3 switch but it is useful to
be able to toggle the switch in/out of reset for the OS.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
This command is useful in U-boot scripts and it is being used by
OpenWrt bootscript for this board [1]. Otherwise shell scripting
commands are enabled by default in cmd/Kconfig.
Tony Dinh [Sun, 17 Apr 2022 20:42:42 +0000 (13:42 -0700)]
arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet
The Zyxel NSA310s board has the network chip Marvell Alaska 88E1318S.
Use uclass mvgbe and the compatible driver M88E1310 driver to bring
up Ethernet.
- Use uclass mvgbe to bring up the network. And remove ad-hoc code.
- Remove CONFIG_RESET_PHY_R.
- Enable CONFIG_PHY_MARVELL to properly configure the network.
- Add phy mode RGMII to kirkwood-nsa310s.dts
- Miscellaneous changes: Move constants to .c file and remove header file
board/zyxel/nsa310s/nsa310s.h, add support for large USB and SATA HDDs,
use BIT macro, add/cleanup comments, and cosmetic changes.
Note that this patch is depended on the following patch:
https://patchwork.ozlabs.org/project/uboot/patch/20220412201820.10291-1-mibodhi@gmail.com/
Tony Dinh [Tue, 12 Apr 2022 20:18:19 +0000 (13:18 -0700)]
net: marvell: mvgbe: Set PHY page 0 before phy_connect
For most Kirkwood boards, the PHY page is already set to page 0
(in register 22) before phy_connect is invoked. But some board like
the Zyxel NSA310S (which uses the network chip MV88E1318S), the PHY page
is not set to page 0. There seems to be some bad data remained in
register 22 when the uclass MVGBE about to invoke phy_connect().
This patch enables the uclass MVGBE to always set the PHY page to 0
before phy_connect.
For reference, please see this discussion:
[RFC PATCH v2] arm: kirkwood: nsa310s: Use Marvell uclass mvgbe
and PHY driver for DM Ethernet.
https://lists.denx.de/pipermail/u-boot/2022-April/480946.html
This patch has been tested with the following Kirkwood boards:
Pali Rohár [Wed, 2 Mar 2022 11:47:58 +0000 (12:47 +0100)]
arm: mvebu: turris_omnia: Add support for USB3.0 mode in WWAN MiniPCIe slot
PCIe Mini CEM 2.1 spec added support for USB3.0 mode on MiniPCIe cards.
USB3.0 and PCIe share same pins and only one function can be active at the
same time. PCIe Mini CEM 2.1 spec says that determining function is
platform specific and spec does not define any dedicated pin which could
say if card is USB3.0-based or PCIe-based.
Implement this platform specific decision (USB3.0 vs PCIe) for WWAN
MiniPCIe slot on Turris Omnia via U-Boot env variable "omnia_wwan_slot",
similarly like is implemented forced mode for MiniPCIe/mSATA slot via
"omnia_msata_slot" env variable. Value "usb3" for "omnia_wwan_slot" would
mean to set USB3.0 mode and value "pcie" original PCIe mode.
A385 SoC on Turris Omnia has configurable fifth SerDes line (exported to
MiniPCIe WWAN slot with SIM card) either to USB3.0 or PCIe functionality,
so implementation of this new PCIe Mini CEM 2.1 feature is simple, by just
configuring SerDes to USB 3.0 mode.
Other twos MiniPCIe slots on Turris Omnia do not have this new
functionality as their SerDes lines cannot be switched to USB3.0
functionality.
Note that A385 SoC does not have too many USB3.0 blocks, so activating
USB3.0 in MiniPCIe cause that one external USB3.0 USB-A port would loose
USB3.0 functionality and would be downgraded just to USB2.0.
By default this MiniPCIe WWAN slot is in PCIe mode, like before.
To set this MiniPCIe WWAN slot to USB3.0 mode, call U-Boot commands:
Pali Rohár [Wed, 2 Mar 2022 11:47:57 +0000 (12:47 +0100)]
arm: mvebu: turris_omnia: Signal error when sata/pcie DT mode
Show error message when DT file does not contain sata or pcie node which
should be explicitly disabled. This can happen when U-Boot code for finding
those nodes is incomplete or when those DT nodes are in different
unexpected location. In any case it is needed to know if DT not was not
explicitly disabled as it could mean that combo slots where setup
incorrectly.
projects / u-boot.git / log
