Simon Glass [Fri, 27 Nov 2015 02:51:20 +0000 (19:51 -0700)]
pci: Refactor the pciinfo() function
This function uses macros to output data. It seems better to use a table of
registers rather than macro-based code generation. It also reduces the
code/data size by 2KB on ARM.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 20 Nov 2015 03:27:02 +0000 (20:27 -0700)]
dm: tegra: pci: Convert tegra boards to driver model for PCI
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Fri, 20 Nov 2015 03:26:58 +0000 (20:26 -0700)]
dm: pci: Support decoding ranges with duplicate entries
At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.
There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).
We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Fri, 20 Nov 2015 03:26:56 +0000 (20:26 -0700)]
dm: pci: Avoid a driver model build error with CONFIG_CMD_PCI_ENUM
This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.
Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
Simon Glass [Sun, 29 Nov 2015 05:16:35 +0000 (22:16 -0700)]
dm: timer: Avoid using timer before it is ready
At present bootstage will try to read the timer very early after relocation.
When driver model is used to provide the timer, we cannot read it until
driver model is ready. Correct this by adding a separate stage for the
post-relocation bootstage init.
This fixes booting on chromebook_link.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Bin Meng [Tue, 24 Nov 2015 20:31:17 +0000 (13:31 -0700)]
dm: timer: Support 64-bit counter
There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 13 Nov 2015 08:11:15 +0000 (00:11 -0800)]
dm: timer: Implement pre_probe()
Every timer device needs to have a valid clock frequency and it
can be specified in the device tree. Use pre_probe() to get this
in the timer uclass driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
Wenyou Yang [Thu, 5 Nov 2015 08:37:53 +0000 (16:37 +0800)]
arm: at91/spl: atmel_sfr: move saic redirect to separate file
To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c
Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Remove the security peripheral select code, keep the default value
in these registers, that is, the peripheral address space is
configured as "Secured" access, it is suitable for SPL.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Thu, 5 Nov 2015 08:37:49 +0000 (16:37 +0800)]
arm: at91/spl: matrix: move matrix init to separate file
To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Wenyou Yang [Fri, 30 Oct 2015 01:55:52 +0000 (09:55 +0800)]
arm: atmel: Add SAMA5D2 Xplained board
The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
York Sun [Wed, 25 Nov 2015 22:56:40 +0000 (14:56 -0800)]
armv8: fsl-layerscape: Fix early MMU table for nand boot
The early MMU table doesn't enable all addresses. Unused addresses
are marked as invalid, as introduced by commit 9979922. An entry
was missing for NAND flash space, causing nand boot failure.
Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
Alison Wang [Fri, 13 Nov 2015 08:49:06 +0000 (16:49 +0800)]
armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and ethaddr
As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shaohui Xie [Tue, 10 Nov 2015 11:16:33 +0000 (19:16 +0800)]
net: phy: added aquantia PHY AQR405 support
The phy can share driver with other aquantia PHYs, so we only
add PHY ID.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
board/ls2080qds: Fix typo in README for QSGMII riser card
DPMACx to PHY mapping for SGMII is mentioned as QSGMII.
So fix typo in README for QSGMII rise card.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Change from ls2085aqds to ls2080aqds] Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Thu, 5 Nov 2015 03:16:26 +0000 (11:16 +0800)]
arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
This patch is to update fdt_high and initrd_high for LS1021AQDS board.
Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
York Sun [Thu, 12 Nov 2015 20:38:21 +0000 (12:38 -0800)]
armv8: fsl-layerscape: Fix "cpu release" command
When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Alison Wang [Thu, 5 Nov 2015 03:15:49 +0000 (11:15 +0800)]
armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
York Sun [Wed, 4 Nov 2015 17:53:10 +0000 (09:53 -0800)]
drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Mingkai Hu [Wed, 11 Nov 2015 09:58:34 +0000 (17:58 +0800)]
pci/layerscape: add support for LS1043A PCIe LUT register access
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list] Reviewed-by: York Sun <yorksun@freescale.com>
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"
Updating the DPNI Eth driver to comply with the restriction.
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Add following debug information in the driver
- Get various DPNI counter values
- Get link status of DPNI objects
- Get information of both ends of connection (DPMAC - DPNI)
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.
Use DPMAC as net device where it represents physical lane.
Below modification done in driver
- Use global DPNI object
- Connect DPMAC to DPNI
- Create and destroy DPMAC
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Tue, 4 Aug 2015 01:55:37 +0000 (09:55 +0800)]
arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
To fix the above issue, the generic physical timer is disabled
before jumping to the OS.
Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: York Sun <yorksun@freescale.com>
Alison Wang [Wed, 15 Jul 2015 07:13:05 +0000 (15:13 +0800)]
arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value. This causes the timer compare to fire 344 seconds
after u-boot configures it. Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.
Signed-off-by: Chris Kilgour <techie@whiterocker.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Marek Vasut [Mon, 23 Nov 2015 16:06:27 +0000 (17:06 +0100)]
arm: socfpga: Repair SoCrates board
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
Dinh Nguyen [Mon, 23 Nov 2015 23:27:17 +0000 (17:27 -0600)]
ARM: socfpga: rename the cyclone5 and arria5 base address file
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
arm: socfpga: reset: FIX address of tstscratch register
The Cyclone V Hard Processor System Technical Reference Manual in the
chapter about the Reset Manager Module Address Map stats that the offset
of the tstscratch register ist 0x54 not 0x24.
Cyclone V Hard Processor System Technical Reference Manual cv_5v4 2015.11.02
page 3-17 Reset Manager Module Address Map
Signed-off-by: Philipp Rosenberger <ilu@linutronix.de>
Thomas Chou [Sat, 31 Oct 2015 03:09:36 +0000 (11:09 +0800)]
cfi_flash: give default CONFIG_SYS_MAX_FLASH_SECT in flash.h
Give default CONFIG_SYS_MAX_FLASH_SECT in flash.h, so that
the header can be included regardless of the present of flash.
The value 512 is the most used.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk [Tue, 24 Nov 2015 19:46:45 +0000 (20:46 +0100)]
PPC4xx: Create "liebherr" vendor directory
In preparation of some new Liebherr boards to be added soon, a new
"liebherr" vendor directory gets created, and the "lwmon5" board
directory is moved into this new vendor directory.
cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Peng Fan [Fri, 27 Nov 2015 02:00:10 +0000 (10:00 +0800)]
video: ipu: fix out of bounds access
We need to access reg stp_rep9, but not stp_rep[(9 - 1) / 2].
If using "__raw_writel(0, DI_STP_REP(disp, 9))", this will exceeds
the size of stp_rep array.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Liu Ying <Ying.Liu@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de>
Reinhard Pfau [Sun, 29 Nov 2015 14:52:14 +0000 (15:52 +0100)]
tools/kwbimage: fix size computations for v1 images
Fix computation of haeder size and binary header size.
Size of opt header and some 32bit values were not taken into account. This could
result in invalid boot images (due to the wrong binary header size, the image could
claim to have another extension header after the binary extension although there
is none).
Use "uint32_t" instead of "unsigned int" for header size computation.
Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Tue, 24 Nov 2015 08:14:59 +0000 (09:14 +0100)]
tools/kwbimage.c: Make sure that the resulting image is 4-byte aligned
With the dtb added to the main U-Boot image, it can happen, that
the resulting image is not 4-byte aligned. As the dtb tends to
be unaligned. But the image needs to be 4-byte aligned. At least the
Marvell hdrparser tool complains if its unaligned. By returning 1 here
in kwbimage_generate(), called via tparams->vrec_header() in mkimage.c,
mkimage will automatically pad the resulting image to a 4-byte size
if necessary.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
Stefan Roese [Tue, 24 Nov 2015 08:15:22 +0000 (09:15 +0100)]
arm: mvebu: Configure ARP timeout and retry count
As some MVEBU platforms using the MVNETA driver seem to miss the
first ARP packet, lets reduce the timeout and increase the retry
count. This increases the speed for communication establishment.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
Bin Meng [Wed, 25 Nov 2015 13:34:54 +0000 (05:34 -0800)]
sf: Move SPI flash drivers to defconfig
There are already Kconfig options for SPI flash drivers, but we
have not moved them from config.h to defconfig files. This commit
does this in a batch.
Vignesh R [Fri, 20 Nov 2015 10:37:41 +0000 (16:07 +0530)]
am33xx: Remove serial_init in s_init for QSPI/NOR XIP boot
serial_init() reads global_data, since global_data is not yet
initialized, this can cause unwanted behaviour leading to QSPI XIP boot
hang. Also, since serial_init() is anyways called later from
boar_init_f(), it does not make sense to do the same in s_init().
Tested on AM437x IDK EVM with QSPI XIP boot.
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
fs: ext4: Prevent infinite loop in ext4fs_iterate_dir
If the ext3 journal gets out of sync with what is written on disk, for
example because of an unexpected power cut, ext4fs_read_file can
return an all-zero directory entry. In that case, ext4fs_iterate_dir
would infinite loop.
This patch detects when a directory entry's direntlen member is 0 and
returns a failure status, which breaks out of the infinite loop. As a
result, U-Boot will not find files that may subsequently be recovered
when the journal is replayed.
This is better behaviour than hanging in an infinite loop, but as a
further improvement maybe U-Boot could interpret the ext3 journal and
actually find the unsynced entries.
Signed-off-by: Thomas Fitzsimmons <fitzsim@cisco.com> Reviewed-by: Stefan Roese <sr@denx.de>
Marcel Ziswiler [Wed, 18 Nov 2015 14:05:06 +0000 (15:05 +0100)]
pci: fix address range check in __pci_hose_phys_to_bus()
The address range check may overflow if the memory region is located at
the top of the 32-bit address space. This can e.g. be seen on TK1 if
using the E1000 gigabit Ethernet driver where start and size are both
0x80000000 leading to the following messages:
Apalis TK1 # tftpboot $loadaddr test_file
Using e1000#0 device
TFTP from server 192.168.10.1; our IP address is 192.168.10.2
Filename 'test_file'.
Load address: 0x80408000
Loading: pci_hose_phys_to_bus: invalid physical address
This patch fixes this by changing the order of the addition vs.
subtraction in the range check just like already done in
__pci_hose_bus_to_phys().
Reported-by: Ivan Mercier <ivan.mercier@nexvision.fr> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Patrick Delaunay [Tue, 17 Nov 2015 10:36:52 +0000 (11:36 +0100)]
part:efi: add bootable parameter in gpt command
The optional parameter bootable is added in gpt command to set the
partition attribute flag "Legacy BIOS bootable"
This flag is used in extlinux and so in with distro to select
the boot partition where is located the configuration file
(please check out doc/README.distro for details).
With this parameter, U-Boot can be used to create the boot partition
needed for device using distro.
Lukasz Majewski [Fri, 20 Nov 2015 07:06:17 +0000 (08:06 +0100)]
gpt: command: Extend gpt command to support GPT table verification
This commit adds support for "gpt verify" command, which verifies
correctness of on-board stored GPT partition table.
As the optional parameter one can provide '$partitons' environment variable
to check if partition data (size, offset, name) is correct.
This command should be regarded as complementary one to "gpt restore".
projects / u-boot.git / log
