From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Date: Thu, 25 Aug 2022 12:59:01 +0000 (-0600)
Subject: spi: zynqmp_gqspi: Add tap delays for Versal
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=f4f1b65cc6b01a787b5efa61bb9be195254d0334;p=u-boot.git

spi: zynqmp_gqspi: Add tap delays for Versal

Add tap delays for Versal platform and re-align the tapdelays code.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index c772bae3cc..958432c08d 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -22,6 +22,7 @@
 #include <dm/device_compat.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
+#include <zynqmp_firmware.h>
 
 #define GQSPI_GFIFO_STRT_MODE_MASK	BIT(29)
 #define GQSPI_CONFIG_MODE_EN_MASK	(3 << 30)
@@ -102,8 +103,10 @@
 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE	0x1
 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT	2
 #define GQSPI_DATA_DLY_ADJ_OFST		0x000001F8
-#define IOU_TAPDLY_BYPASS_OFST		0xFF180390
+#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
+				0xFF180390 : 0xF103003C
 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK	0x00000020
+#define GQSPI_FREQ_37_5MHZ		37500000
 #define GQSPI_FREQ_40MHZ		40000000
 #define GQSPI_FREQ_100MHZ		100000000
 #define GQSPI_FREQ_150MHZ		150000000
@@ -297,28 +300,41 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval)
 	debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
 	      __func__, reqhz, clk_rate, baudrateval);
 
-	if (reqhz < GQSPI_FREQ_40MHZ) {
-		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
-		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
-				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
-	} else if (reqhz <= GQSPI_FREQ_100MHZ) {
-		zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
-		tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
-				TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
-		lpbkdlyadj = readl(&regs->lpbkdly);
-		lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
-		datadlyadj = readl(&regs->gqspidlyadj);
-		datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
-				| (GQSPI_DATA_DLY_ADJ_VALUE <<
-					GQSPI_DATA_DLY_ADJ_SHIFT));
-	} else if (reqhz <= GQSPI_FREQ_150MHZ) {
-		lpbkdlyadj = readl(&regs->lpbkdly);
-		lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
-				GQSPI_LPBK_DLY_ADJ_DLY_0);
+	if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
+		if (reqhz <= GQSPI_FREQ_40MHZ) {
+			tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+					TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
+			tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+					TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+			lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+			datadlyadj = (GQSPI_USE_DATA_DLY <<
+				      GQSPI_USE_DATA_DLY_SHIFT) |
+				       (GQSPI_DATA_DLY_ADJ_VALUE <<
+					GQSPI_DATA_DLY_ADJ_SHIFT);
+		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
+			lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+				      GQSPI_LPBK_DLY_ADJ_DLY_0;
+		}
+		zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
+				  IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
+	} else {
+		if (reqhz <= GQSPI_FREQ_37_5MHZ) {
+			tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+					TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+		} else if (reqhz <= GQSPI_FREQ_100MHZ) {
+			tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+					TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+			lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+			datadlyadj = GQSPI_USE_DATA_DLY <<
+				      GQSPI_USE_DATA_DLY_SHIFT;
+		} else if (reqhz <= GQSPI_FREQ_150MHZ) {
+			lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+				      (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
+				       GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
+		}
+		writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
 	}
-
-	zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
-			  tapdlybypass);
 	writel(lpbkdlyadj, &regs->lpbkdly);
 	writel(datadlyadj, &regs->gqspidlyadj);
 }