From: Minda Chen Date: Mon, 7 Aug 2023 08:53:37 +0000 (+0800) Subject: riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=eca2d41c681466c229fc0b4372432db71745c826;p=u-boot.git riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive SYS_CACHE_SHIFT_6 to enable it. Signed-off-by: Minda Chen Reviewed-by: Bin Meng Reviewed-by: Leo Yu-Chi Liang --- diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d9581165b..c1d3e6ada2 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SYS_CACHE_SHIFT_6 select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD