From: Peng Fan <peng.fan@nxp.com>
Date: Sun, 6 Oct 2024 00:22:51 +0000 (+0800)
Subject: misc: ele_mu: Clear RR when initialize MU
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=e7431340743962b4cfaffda95016c55bd2df297a;p=u-boot.git

misc: ele_mu: Clear RR when initialize MU

When OS is doing ELE API call, before OS get the response, OS is force
reseted, then it is possible that MU RR has data during initialization
in SPL stage. So clear the RR registers, otherwise SPL ELE API call will
work abnormal.

Cc: Alice Guo <alice.guo@nxp.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index f5ba3a4ffa..cdb85b999d 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -25,9 +25,20 @@ struct imx8ulp_mu {
 void mu_hal_init(ulong base)
 {
 	struct mu_type *mu_base = (struct mu_type *)base;
+	u32 rr_num = (readl(&mu_base->par) & 0xFF00) >> 8;
+	int i;
 
 	writel(0, &mu_base->tcr);
 	writel(0, &mu_base->rcr);
+
+	while (true) {
+		/* If there is pending RX data, clear them by read them out */
+		if (!(readl(&mu_base->sr) & BIT(6)))
+			return;
+
+		for (i = 0; i < rr_num; i++)
+			readl(&mu_base->rr[i]);
+	}
 }
 
 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)