From: Tanmay Shah <tanmay.shah@amd.com>
Date: Mon, 4 Dec 2023 21:56:18 +0000 (-0800)
Subject: mailbox: add el3 support only for zynqmp platform
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=e2c3e9c2b1dda376c10e991af5ead7404a240682;p=u-boot.git

mailbox: add el3 support only for zynqmp platform

If U-Boot is running in Exception Level 3 then use hardcode
register values for mailbox message passing with PMU.
This is only supported for zynqmp platform.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Link: https://lore.kernel.org/r/20231204215620.63334-3-tanmay.shah@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c
index acd0b287db..e76561f310 100644
--- a/drivers/mailbox/zynqmp-ipi.c
+++ b/drivers/mailbox/zynqmp-ipi.c
@@ -81,6 +81,7 @@ struct zynqmp_ipi {
 	void __iomem *remote_res_regs;
 	u32 remote_id;
 	u32 local_id;
+	bool el3_supported;
 };
 
 static int zynqmp_ipi_fw_call(struct zynqmp_ipi *ipi_mbox,
@@ -115,6 +116,12 @@ static int zynqmp_ipi_send(struct mbox_chan *chan, const void *data)
 		return ret;
 	}
 
+	/* Return if EL3 is not supported */
+	if (!zynqmp->el3_supported) {
+		dev_err(chan->dev, "mailbox in EL3 only supported for zynqmp");
+		return -EOPNOTSUPP;
+	}
+
 	/* Write trigger interrupt */
 	writel(IPI_BIT_MASK_PMU0, &ipi_int_apu->trig);
 
@@ -159,6 +166,9 @@ static int zynqmp_ipi_probe(struct udevice *dev)
 
 	debug("%s(dev=%p)\n", __func__, dev);
 
+	if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
+		zynqmp->el3_supported = true;
+
 	/* Get subnode where the regs are defined */
 	/* Note IPI mailbox node needs to be the first one in DT */
 	node = ofnode_first_subnode(dev_ofnode(dev));