From: Pali Rohár Date: Fri, 24 Sep 2021 20:59:22 +0000 (+0200) Subject: arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=de7293043329c6d230b7f81861867c6a645f4dc7;p=u-boot.git arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h index 55a4c267c4..64193d5288 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h +++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h @@ -12,7 +12,7 @@ /* Direct access to PEX0 Root Port's PCIe Capability structure */ #define PEX0_RP_PCIE_CFG_OFFSET (0x00080000 + 0x60) -/* PEX_CAPABILITIES_REG fields */ +/* SOC_CONTROL_REG1 fields */ #define PCIE0_ENABLE_OFFS 0 #define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS) #define PCIE1_ENABLE_OFFS 1