From: York Sun <yorksun@freescale.com>
Date: Tue, 6 Jan 2015 21:18:52 +0000 (-0800)
Subject: driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation
X-Git-Tag: v2025.01-rc5-pxa1908~13721^2~20
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=dc1437afd761e83497d94eae0d6dcc2c2ff4711f;p=u-boot.git

driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation

wwt_bg should match rrt_bg. It was a typo in driver.

Signed-off-by: York Sun <yorksun@freescale.com>
---

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 713c3ed761..690e73dacf 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1928,7 +1928,7 @@ static void set_timing_cfg_8(const unsigned int ctrl_num,
 		wwt_bg = tccdl - 4;
 	} else {
 		rrt_bg = tccdl - 2;
-		wwt_bg = tccdl - 4;
+		wwt_bg = tccdl - 2;
 	}
 
 	acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);