From: Ye Li <ye.li@nxp.com>
Date: Fri, 28 Apr 2023 04:08:45 +0000 (+0800)
Subject: imx9: Calculate DDR size from DDRC setting
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=dace5e9fdc17786a3c4a857e63032d7d012e316d;p=u-boot.git

imx9: Calculate DDR size from DDRC setting

To avoid using static setting for ECC enabled DDR size, switch
to calculate DDR size from DDRC setting

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 6ae7e70489..64e8ac610e 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -36,6 +36,7 @@
 #include <asm/arch-imx/cpu.h>
 #include <asm/mach-imx/s400_api.h>
 #include <fuse.h>
+#include <asm/arch/ddr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -327,14 +328,26 @@ void enable_caches(void)
 
 __weak int board_phys_sdram_size(phys_size_t *size)
 {
+	phys_size_t start, end;
+	phys_size_t val;
+
 	if (!size)
 		return -EINVAL;
 
-	*size = PHYS_SDRAM_SIZE;
+	val = readl(REG_DDR_CS0_BNDS);
+	start = (val >> 16) << 24;
+	end   = (val & 0xFFFF);
+	end   = end ? end + 1 : 0;
+	end   = end << 24;
+	*size = end - start;
+
+	val = readl(REG_DDR_CS1_BNDS);
+	start = (val >> 16) << 24;
+	end   = (val & 0xFFFF);
+	end   = end ? end + 1 : 0;
+	end   = end << 24;
+	*size += end - start;
 
-#ifdef PHYS_SDRAM_2_SIZE
-	*size += PHYS_SDRAM_2_SIZE;
-#endif
 	return 0;
 }