From: mingming lee Date: Tue, 31 Dec 2019 03:29:26 +0000 (+0800) Subject: ARM: MediaTek: add basic support for MT8512 boards X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=b9bf3cbfd613099d15122140faddf632ae9d1165;p=u-boot.git ARM: MediaTek: add basic support for MT8512 boards This adds a general board file based on MT8512 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. This commit is adding the basic boot support for the MT8512 eMMC board. Signed-off-by: mingming lee --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d7e625ef1d..3c7ecd2e8f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -874,6 +874,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ + mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts new file mode 100644 index 0000000000..296ed93b9e --- /dev/null +++ b/arch/arm/dts/mt8512-bm1-emmc.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee + * + */ + +/dts-v1/; + +#include +#include "mt8512.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "MT8512 BM1 EMMC"; + + chosen { + stdout-path = &uart0; + tick-timer = &timer0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x20000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; + +&pinctrl { + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; + groups = "msdc0"; + }; + + conf-cmd-data { + pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1", + "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4", + "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7"; + input-enable; + drive-strength = <6>; + bias-pull-up; + }; + + conf-clk { + pins = "MSDC0_CLK"; + drive-strength = <6>; + bias-pull-down; + }; + + conf-rst { + pins = "MSDC0_RSTB"; + bias-pull-up; + }; + }; + + uart0_pins: uart0 { + mux { + function = "uart"; + groups = "uart0_0_rxd_txd"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig new file mode 100644 index 0000000000..87bd1fbe69 --- /dev/null +++ b/board/mediatek/mt8512/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MT8512 + +config SYS_BOARD + default "mt8512" + +config SYS_CONFIG_NAME + default "mt8512" + + +config MTK_BROM_HEADER_INFO + string + default "media=nor" + +endif diff --git a/board/mediatek/mt8512/MAINTAINERS b/board/mediatek/mt8512/MAINTAINERS new file mode 100644 index 0000000000..966b1a749d --- /dev/null +++ b/board/mediatek/mt8512/MAINTAINERS @@ -0,0 +1,6 @@ +MT8512 +M: Mingming lee +S: Maintained +F: board/mediatek/mt8512 +F: include/configs/mt8512.h +F: configs/mt8512_bm1_emmc_defconfig diff --git a/board/mediatek/mt8512/Makefile b/board/mediatek/mt8512/Makefile new file mode 100644 index 0000000000..c1f596b39d --- /dev/null +++ b/board/mediatek/mt8512/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt8512.o diff --git a/board/mediatek/mt8512/mt8512.c b/board/mediatek/mt8512/mt8512.c new file mode 100644 index 0000000000..726111d7d3 --- /dev/null +++ b/board/mediatek/mt8512/mt8512.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->ram_base + 0x100; + + debug("gd->fdt_blob is %p\n", gd->fdt_blob); + return 0; +} diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig new file mode 100644 index 0000000000..ee3b8e1ed1 --- /dev/null +++ b/configs/mt8512_bm1_emmc_defconfig @@ -0,0 +1,44 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_SYS_TEXT_BASE=0x44e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_TARGET_MT8512=y +CONFIG_SYS_PROMPT="MT8512> " +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_LIBFDT=y +# CONFIG_FDT_DEBUG is not set +CONFIG_LZMA=y +CONFIG_LZ4=y +CONFIG_LZO=y +CONFIG_GZIP=y +CONFIG_BZIP2=y +CONFIG_CMD_BOOTMENU=y +CONFIG_MENU_SHOW=y +CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" +CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MT8512=y +CONFIG_PINCONF=y +CONFIG_DM_GPIO=y +CONFIG_RAM=y +CONFIG_BAUDRATE=921600 +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_WDT=y +CONFIG_WDT_MTK=y +CONFIG_CLK=y +CONFIG_TIMER=y +CONFIG_MTK_TIMER=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h new file mode 100644 index 0000000000..253a54332c --- /dev/null +++ b/include/configs/mt8512.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee + */ + +#ifndef __MT8512_H +#define __MT8512_H + +#include + +#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M + +#define CONFIG_CPU_ARMV8 + +#define COUNTER_FREQUENCY 13000000 + +#define CONFIG_SYS_LOAD_ADDR 0x41000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_MALLOC_LEN SZ_32M +#define CONFIG_SYS_BOOTM_LEN SZ_64M + +/* Uboot definition */ +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + \ + SZ_2M - \ + GENERATED_GBL_DATA_SIZE) + +/* ENV Setting */ +#if defined(CONFIG_MMC_MTK) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OVERWRITE + +/* MMC offset in block unit,and block size is 0x200 */ +#define ENV_BOOT_READ_IMAGE \ + "boot_rd_img=mmc dev 0" \ + ";mmc read ${loadaddr} 0x27000 0x8000" \ + ";iminfo ${loadaddr}\0" +#endif + +/* Console configuration */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" + +#define ENV_BOOT_CMD \ + "mtk_boot=run boot_rd_img;bootm;\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6c000000\0" \ + ENV_DEVICE_SETTINGS \ + ENV_BOOT_READ_IMAGE \ + ENV_BOOT_CMD \ + "bootcmd=run mtk_boot;\0" \ + +#endif