From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Date: Tue, 10 Sep 2024 09:39:13 +0000 (+0800)
Subject: riscv: Make A ISA extension selectable
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=9c0ed7214298e4d9e575bff0f34ae6cacba8bfc4;p=u-boot.git

riscv: Make A ISA extension selectable

Make the Atomic (A) ISA extension selectable. Thus CPUs such as
Ibex without the A extension can be supported.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016c52..c5859c5c54 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -308,7 +308,10 @@ config TPL_USE_ARCH_STRNCMP
 endmenu
 
 config RISCV_ISA_A
-	def_bool y
+	bool "Standard extension for Atomic Instructions"
+	default y
+	help
+	  Adds "A" to the ISA string passed to the compiler.
 
 config DMA_ADDR_T_64BIT
 	bool