From: Neal Liu <neal_liu@aspeedtech.com>
Date: Tue, 15 Feb 2022 10:14:40 +0000 (+0800)
Subject: crypto: aspeed: fix polling RSA status wrong issue
X-Git-Url: http://git.dujemihanovic.xyz/img/sics.gif?a=commitdiff_plain;h=829b41171b181e083fc984b72bb8acb31c1fb952;p=u-boot.git

crypto: aspeed: fix polling RSA status wrong issue

Check interrupt status to see if RSA engine is completed. After completion
of the task, write-clear the status to finish operation.
Add missing register base for completion.

Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support")
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---

diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c
index c28cdf374b..47a007f633 100644
--- a/drivers/crypto/aspeed/aspeed_acry.c
+++ b/drivers/crypto/aspeed/aspeed_acry.c
@@ -103,7 +103,7 @@ static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t
 	while (1) {
 		reg = readl(acry->base + ACRY_RSA_INT_STS);
 		if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) {
-			writel(reg, ACRY_RSA_INT_STS);
+			writel(reg, acry->base + ACRY_RSA_INT_STS);
 			break;
 		}
 		udelay(20);